Skip to main content
SpringerLink
Log in

Field Programmable Logic and Application

14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings

  • Conference proceedings
  • © 2004

Overview

Editors:
  1. Jürgen Becker

    1. ITIV - Universitaet Karlsruhe (TH),  

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  2. Marco Platzner

    1. University of Paderborn,  

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  3. Serge Vernalde

    1. IMEC, Leuven, Belgium

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3203)

Included in the following conference series:

Conference proceedings info: FPL 2004.

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 74.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (177 papers)

  1. Physical Design 1

    1. Compact Buffered Routing Architecture

      • A. Lodi, R. Giansante, C. Chiesa, L. Ciccarelli, F. Campi, M. Toma
      Pages 179-188

    2. On Optimal Irregular Switch Box Designs

      • Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu
      Pages 189-199

  2. Arithmetic 1

    1. Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation

      • Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
      Pages 200-208

    2. Comparative Study of SRT-Dividers in FPGA

      • Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps
      Pages 209-220

    3. Second Order Function Approximation Using a Single Multiplication on FPGAs

      • Jérémie Detrey, Florent de Dinechin
      Pages 221-230

    4. Efficient Modular Division Implementation

      • Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater
      Pages 231-240

  3. Multitasking

    1. A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management

      • Jesus Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
      Pages 241-250

    2. The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures

      • Sebastian Lange, Martin Middendorf
      Pages 251-260

  4. Circuit Technology

    1. A High-Density Optically Reconfigurable Gate Array Using Dynamic Method

      • Minoru Watanabe, Fuminori Kobayashi
      Pages 261-269

    2. Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device

      • D. Keymeulen, R. Zebulum, A. Stoica, V Duong, M. I. Ferguson
      Pages 270-278

  5. Memory 1

    1. Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA

      • Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agullo, Atilà Herms-Berenguer
      Pages 279-288

    2. Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays

      • Fatih Kocan, Jason Meyer
      Pages 289-300

  6. Network Processing

    1. A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks

      • David V. Schuehler, John W. Lockwood
      Pages 301-310

    2. Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs

      • Zachary K. Baker, Viktor K. Prasanna
      Pages 311-321

  7. Testing

    1. BIST Based Interconnect Fault Location for FPGAs

      • Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko
      Pages 322-332

    2. FPGAs BIST Evaluation

      • A. Parreira, J. P. Teixeira, M. B. Santos
      Pages 333-343

  8. Applications

    1. Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor

      • C. J. Tavares, C. Bungardean, G. M. Matos, J. T. de Sousa
      Pages 344-353

    2. Evaluating Fault Emulation on FPGA

      • Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe
      Pages 354-363

  9. Arithmetic 2

    1. Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs

      • Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk
      Pages 364-373

    2. Multiple Restricted Multiplication

      • Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
      Pages 374-383
Back to top

Other volumes

  1. Field Programmable Logic and Application

Keywords

Editors and Affiliations

  • ITIV - Universitaet Karlsruhe (TH),  

    Jürgen Becker

  • University of Paderborn,  

    Marco Platzner

  • IMEC, Leuven, Belgium

    Serge Vernalde

Bibliographic Information

Publish with us

Policies and ethics

Back to top

Search

Navigation