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Field Programmable Logic and Application

14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004. Proceedings

  • Jürgen Becker
  • Marco Platzner
  • Serge Vernalde

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Table of contents

  1. Network and Optimization Algorithms

    1. Yutaka Sugawara, Mary Inaba, Kei Hiraki
      Pages 484-493
    2. Ma José Canet, Felip Vicedo, Vicenç Almenar, Javier Valls, Eduardo R. de Lima
      Pages 494-504
    3. Yoshiki Yamaguchi, Tsutomu Maruyama, Akihiko Konagaya
      Pages 505-515
    4. Shin’ichi Wakabayashi, Kenji Kikuchi
      Pages 516-525
  2. System-on-Chip 1

    1. Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi et al.
      Pages 526-535
    2. Mark Holland, Scott Hauck
      Pages 536-545
  3. High Speed Design

    1. Daniel Denning, James Irvine, Malachy Devlin
      Pages 546-554
    2. Viktor Fischer, Miloš Drutarovský, Martin Šimka, Nathalie Bochard
      Pages 555-564
  4. Security and Cryptography 2

    1. Norbert Pramstaller, Johannes Wolkerstorfer
      Pages 565-574
    2. Joseph Zambreno, David Nguyen, Alok Choudhary
      Pages 575-585
  5. Architectures 2

  6. Memory 2

    1. Dalia Dagher, Iyad Ouaiss
      Pages 606-616
  7. Image Processing 1

    1. Javier Díaz, Eduardo Ros, Sonia Mota, Richard Carrillo, Rodrigo Agis
      Pages 617-626
    2. Tim Todman, Wayne Luk
      Pages 627-636
  8. Network-on-Chip

    1. T. A. Bartic, D. Desmet, J-Y. Mignolet, T. Marescaux, D. Verkest, S. Vernalde et al.
      Pages 637-647
    2. Christophe Layer, Hans-Jörg Pfleiderer
      Pages 648-657
  9. Power Aware Design 1

  10. IP-Based Design

    1. Holger Lange, Andreas Koch
      Pages 679-689
    2. Claudiu Zissulescu, Bart Kienhuis, Ed Deprettere
      Pages 690-699
    3. Arthur Segard, François Verdier
      Pages 710-718
  11. Power Aware Design 2

    1. Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
      Pages 719-728
    2. Rajarshi Mukherjee, Seda Ogrenci Memik
      Pages 740-750
    3. Michael G. Lorenz, Luis Mengibar, Mario G. Valderas, Luis Entrena
      Pages 751-760
  12. Coprocessing Architectures

    1. M. Petrov, T. Murgan, F. May, M. Vorbach, P. Zipf, M. Glesner
      Pages 761-770
    2. Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek
      Pages 781-790
    3. Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller
      Pages 791-800
  13. Embedded Tutorials

    1. B. Blodget, C. Bobda, M. Huebner, A. Niyonkuru
      Pages 801-810
    2. Adam Donlin, Axel Braun, Adam Rose
      Pages 811-820
    3. Jim Torresen
      Pages 821-830
  14. Dynamic Reconfiguration 2

    1. Herbert Walder, Marco Platzner
      Pages 831-835
    2. Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri
      Pages 836-841
    3. Björn Griese, Erik Vonnahme, Mario Porrmann, Ulrich Rückert
      Pages 842-846
  15. Physical Design 2

    1. Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan C. van der Veen
      Pages 847-851
    2. Shawn Phillips, Akshay Sharma, Scott Hauck
      Pages 857-861
  16. Acceleration Application 2

    1. Tom Van Court, Yongfeng Gu, Martin Herbordt
      Pages 862-867
    2. M. D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, C. E. Goutis
      Pages 868-873
    3. Cristinel Ababei, Pongstorn Maidee, Kia Bazargan
      Pages 874-880
  17. System Level Design

    1. Yang Qu, Kari Tiensyrjä, Kostas Masselos
      Pages 881-885
  18. Physical Interconnect

    1. Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alex Nicolau, Rajesh Gupta
      Pages 891-899
    2. Renqiu Huang, Manish Handa, Ranga Vemuri
      Pages 900-905
  19. Computational Models

    1. Hossam ElGindy, George Ferizis
      Pages 906-910
    2. Takehiro Ito, Yuichiro Shibata, Kiyoshi Oguri
      Pages 911-916
  20. Acceleration Applications 3

    1. Martin Schoeberl
      Pages 917-921

About these proceedings

Keywords

Alignment Computer Java SoC algorithms cryptographic implementations field-programmable logic logic operating system optimization power-aware design reconfigurable computing reconfigurable logic system-on-chip systems level design

Editors and affiliations

  • Jürgen Becker
    • 1
  • Marco Platzner
    • 2
  • Serge Vernalde
    • 3
  1. 1.ITIV - Universitaet Karlsruhe (TH) 
  2. 2.University of Paderborn 
  3. 3.IMECLeuvenBelgium

Bibliographic information

  • DOI https://doi.org/10.1007/b99787
  • Copyright Information Springer-Verlag Berlin Heidelberg 2004
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-22989-6
  • Online ISBN 978-3-540-30117-2
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site