On Optimal Irregular Switch Box Designs
In this paper, we develop a unified theory in analyzing optimal switch box design problems, particularly for the unsolved irregular cases, where different pin counts are allowed on different sides. The results drawn from our system of linear Diophantine equations based formulation turn out to be general. We prove that the divide-and-conquer (reduction) design methodology can also be applied to the irregular cases. Namely, an optimal arbitrarily large irregular or regular switch box can be obtained by combining small prime switch boxes, which largely reduces the design complexity. We revise the known VPR router for our experiments and show that the design optimality of switch boxes does pay off.
KeywordsConfigurable computing on-chip network FPGA switch box
Unable to display preview. Download preview PDF.
- 1.Betz, V., Rose, J.: Directional bias and non-uniformity in FPGA global routing architectures. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Washington, November 10-14, pp. 652–659. IEEE Computer Society Press, Los Alamitos (1996)Google Scholar
- 2.Betz, V., Rose, J.: A New Packing, Placement and Routing Tool for FPGA Research. In: Seventh International Workshop on Field-Programmable Logic and Applications, pp. 213–222 (1997)Google Scholar
- 3.Betz, V., Rose, J., Marquardt, A.: Architecure and CAD for Deep-Submicron FPGAs. Kluwer-Academic Publisher, Boston (1999)Google Scholar
- 8.Fan, H., Liu, J., Wu, Y.L., Cheung, C.C.: On optimum switch box designs for 2-D FPGAs. In: Proceedings of the 2001 Design Automation Conference (DAC 2001), June 18-22, pp. 203–208. ACM Press, New York (2001)Google Scholar
- 10.Hallschmid, P., Wilton, S.: Detailed routing architectures for embedded programmable logic IP cores. In: The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2001, pp. 69–74 (2001)Google Scholar
- 13.Shyu, M., Wu, G.M., Chang, Y.D., Chang, Y.W.: Generic Universal Switch Blocks. IEEE Trans. on Computers, 348–359 (April 2000)Google Scholar
- 14.Wilton, S.J.: Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory. PhD thesis, University of Toronto (1997)Google Scholar