A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management

  • Jesus Tabero
  • Julio Septién
  • Hortensia Mecha
  • Daniel Mozos
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


A novel technique is proposed for the management of a two-dimensional run-time reconfigurable device in order to get true hardware multitasking. The proposed technique uses a Vertex List Set to keep track of the available free area, and of the candidate locations to place the arriving tasks. Each Vertex List describes the contour of each unoccupied area fragment in the reconfigurable device. Several heuristics are proposed to solve the problem of selecting one of the vertices to place the task. The heuristic that gives best results is based on a novel fragmentation metric. This metric estimates for each alternative location the suitability of the resulting free device area to accept future incoming tasks. Finally, we show that our approach, with a reasonable complexity, gives better results, in terms of device fragmentation and efficiency, than other techniques.


Free Area Task Placement Reconfigurable Computing Candidate Vertex Feasible Location 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Compton, K., Hauck, S.: Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Surveys 34(2), 171–210 (2002)CrossRefGoogle Scholar
  2. 2.
    Diessel, O.F., Wigley, G.: Opportunities for Operating Systems Research in Reconfigurable Computing. Technical report ACRC-99-018. Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia (1999)Google Scholar
  3. 3.
    Diessel, O.F., Elgindy, H.: On Dynamic Task Scheduling for FPGA-based Systems. International Journal of Foundations of Computer Science, IJFCS 2001 12(5) (2001)Google Scholar
  4. 4.
    Bazargan, K., Kastner, R., Sarrafzadeh, M.: Fast Template Placement for Reconfigurable Computing Systems. IEEE Design and Test of Computers 17, 68–83 (2000)CrossRefGoogle Scholar
  5. 5.
    Walder, H., Platzner, M.: Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: ERSA 2002, Las Vegas, US, June 2002, pp. 24–30 (2002)Google Scholar
  6. 6.
    Walder, H., Steiger, C., Platzner, M.: Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing. In: RAW 2003, Munich, Germany (April 2003)Google Scholar
  7. 7.
    Steiger, C., Walder, H., Platzner, M., Thiele, L.: Online Scheduling and Placement of Realtime Tasks to Partially Reconfigurable Devices. In: RTSS 2003, Cancun, Mexico (December 2003)Google Scholar
  8. 8.
    Coffman, E., Csirik, J., Woeginger, G.: Approximate Solutions to Bin-Packing Problems. In: Pardalos, P., Resende, M. (eds.) Handbook of Applied Optimization, Oxford University Press, Oxford (2002)Google Scholar
  9. 9.
    Tabero, J., Septién, J., Mecha, H., Mozos, D.: A vertex-list approach to 2D HW multitasking management in RTR FPGAs., In: DCIS 2003, Ciudad Real, Spain, pp. 545–550 (November 2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Jesus Tabero
    • 1
  • Julio Septién
    • 2
  • Hortensia Mecha
    • 2
  • Daniel Mozos
    • 2
  1. 1.Instituto Nacional de Técnica AeroespacialMadridSpain
  2. 2.Universidad Complutense de MadridMadridSpain

Personalised recommendations