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Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA

  • Eduardo Picatoste-Olloqui
  • Francisco Cardells-Tormo
  • Jordi Sempere-Agullo
  • Atilà Herms-Berenguer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

This paper deals with the FPGA-implementation of a high-speed interface for DDR SDRAMs. We aim to achieve a performance, in terms of bandwidth, comparable to ASIC implementations. The novelty of this paper is to present the design techniques that lead to high performance memory controllers. First of all, we compile the specific hardware features available in FPGA families. In the second place, we depict a memory interface data path architecture adapted for implementation on Xilinx and Altera FPGAs. Finally, we explain the design rules to meet timing requirements (round trip delay) for successful operation. The discussion is complemented with timing measurements for a Virtex-II based memory interface and with timing calculations performed for Stratix.

Keywords

Data Path Memory Controller Memory Interface Round Trip Delay Xilinx FPGAs 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Ryan, K.: DDR SDRAM Functionality and Controller Read Data Capture. Micron Design Line 8(3) (1999)Google Scholar
  2. 2.
    JEDEC: JEDEC Standard Double Data Rate (DDR) SDRAM Specification, JESD79. Available on-line (2002) Google Scholar
  3. 3.
    Altera Corp.: DDR SDRAM Controller MegaCore Function User Guide. Available on-line (2004) Google Scholar
  4. 4.
    Northwest Logic: DDR SDRAM Controller. Datasheet. Available on-line (2004) Google Scholar
  5. 5.
    Tran, J.: Synthesizable DDR SDRAM Controller. Xilinx Application Note XAPP200. Available on-line (2003) Google Scholar
  6. 6.
    Altera Corp.: Using the Stratix and Stratix GX DDR Round Trip Delay (RTD) Calculator. Available from Altera under request (2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Eduardo Picatoste-Olloqui
    • 1
  • Francisco Cardells-Tormo
    • 1
  • Jordi Sempere-Agullo
    • 1
    • 2
  • Atilà Herms-Berenguer
    • 2
  1. 1.Hewlett-Packard, R&D Technology Lab., Digital ASICsSant Cugat del Valles (Barcelona)Spain
  2. 2.Department of ElectronicsUniversity of Barcelona (UB)BarcelonaSpain

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