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BIST Based Interconnect Fault Location for FPGAs

  • Nicola Campregher
  • Peter Y. K. Cheung
  • Milan Vasilko
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defect knowledge during manufacturing test to classify faulty devices into different defect groups. A Built-In Self-Test (BIST) method that can efficiently identify the exact location of the interconnect fault is introduced. This procedure forms the first step of a new interconnect defect tolerant scheme that offers the possibility of using larger and more cost effective devices that contain interconnect defects without compromising on performance or configurability.

Keywords

Clock Cycle Test Vector Switch Matrix FPGA Architecture Switch Matrice 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Nicola Campregher
    • 1
  • Peter Y. K. Cheung
    • 1
  • Milan Vasilko
    • 2
  1. 1.Department of EEEImperial CollegeLondonUK
  2. 2.School of Design, Engineering and ComputingBournemouth UniversityUK

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