BIST Based Interconnect Fault Location for FPGAs

  • Nicola Campregher
  • Peter Y. K. Cheung
  • Milan Vasilko
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defect knowledge during manufacturing test to classify faulty devices into different defect groups. A Built-In Self-Test (BIST) method that can efficiently identify the exact location of the interconnect fault is introduced. This procedure forms the first step of a new interconnect defect tolerant scheme that offers the possibility of using larger and more cost effective devices that contain interconnect defects without compromising on performance or configurability.


Clock Cycle Test Vector Switch Matrix FPGA Architecture Switch Matrice 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Brown, S.D., Francis, R.J., Rose, J., Vranesic, Z.G.: Field Programmable Gate Arrays. Kluwer, Norwell (1992)zbMATHGoogle Scholar
  2. 2.
    Hanchek, F., Dutt, S.: Methodologies for tolerating cell and interconnect faults in FPGAs. IEEE Transactions on Computers 47(1), 15–33 (1998)CrossRefGoogle Scholar
  3. 3.
    Stroud, C., Wijesuriya, S., Hamilton, C., Abramovici, M.: Built in self test of FPGA interconnect. In: Proc. Int. Test Conf., pp. 404–411 (1998)Google Scholar
  4. 4.
    Renovell, M., Figueras, J., Zorian, Y.: Test of RAM-based FPGA: Methodology and application to the interconnect structure. In: Proc. 15th IEEE Very Large Scale Integration (VLSI) Test Symp., pp. 204–209 (1997)Google Scholar
  5. 5.
    Renovell, M., Portal, J.M., Figueras, J., Zorian, Y.: Testing the interconnect of RAM-based FPGAs. IEEE Des. Test Comput., 45–50 (1998)Google Scholar
  6. 6.
    Michinishi, H., Yokohira, T., Okamoto, T., Inoue, T., Fujiwara, H.: Test methodology for interconnect structures of LUT-based FPGAs. In: Proc. 5th Asian Test Symp., pp. 68–74 (1996)Google Scholar
  7. 7.
    Niamat, M.Y., Nambiar, R., Jamall, M.M.: A BIST Scheme for testing the interconnect of SRAM based FPGAs. In: The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002, vol. 2, pp. 41–44 (2002)Google Scholar
  8. 8.
    Harris, I.G., Tessier, R.: Testing and diagnosis of interconnect faults in clusterbased FPGA architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, 1337–1343 (2002)CrossRefGoogle Scholar
  9. 9.
    Liu, J., Simmons, S.: BIST diagnosis of interconnects fault locations in FPGA’s. In: Canadian Conference on Electrical and Computer Engineering, 2003. IEEE CCECE 2003, May 4-7, vol. 1, pp. 207–210 (2003)Google Scholar
  10. 10.
    Sun, X., Xu, S., Xum, J., Trouborst, P.: Design and implementation of a paritybased BIST scheme for FPGA global interconnects. In: CCECE (2001)Google Scholar
  11. 11.
    Xilinx Inc., The Reliability Report (September 2003)Google Scholar
  12. 12.
    Xilinx Inc., Virtex II Pro Platform FPGA Handbook (October 2002)Google Scholar
  13. 13.
    Alter Corp., Stratix II Device Handbook (February 2004)Google Scholar
  14. 14.
    Xilinx Inc., Virtex II Pro EasyPath Solutions (2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Nicola Campregher
    • 1
  • Peter Y. K. Cheung
    • 1
  • Milan Vasilko
    • 2
  1. 1.Department of EEEImperial CollegeLondonUK
  2. 2.School of Design, Engineering and ComputingBournemouth UniversityUK

Personalised recommendations