Advertisement

Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays

  • Fatih Kocan
  • Jason Meyer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

In this paper, we propose a new area-efficient logic module architecture for SRAM-based FPGAs. This new architecture is motivated by the analysis results of some LUT-level benchmarks. The analysis results indicate that a large percentage of the LUTs in a LUT-level circuit are permutation (P) equivalent (not even including input negations or output negations, called NPN equivalences in the literature, or constant assignments). The proposed logic module utilizes lookup table sharing among two or more basic logic elements (BLEs) in a cluster, as opposed to one LUT per BLE. Preliminary results indicate that almost half of the LUTs are eliminated in all benchmarks. This great area reduction would reflect to the cost and prices of FPGAs and also would strengthen the FPGA usage in applications that have rigid area constraints such as an FPGA within a hearing aid.

Keywords

Logic Module Critical Path Truth Table Logic Block Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Agrawal, O., Chang, H., Sharpe-Geisler, B., Schmitz, N., Nguyen, B., Wong, J., Tran, G., Fontana, F., Harding, B.: An innovative, segmented high performance fpga family with variable-grain-architecture and wide-gating functions. In: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, Monterey, California, pp. 17–26 (1999)Google Scholar
  2. 2.
    Ahmed, E., Rose, J.: The effect of lut and cluster size on deep-submicron fpga performance and density. In: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, Monterey, California, pp. 3–12 (2000)Google Scholar
  3. 3.
    Altera. Programmable Logic Data Book (1996)Google Scholar
  4. 4.
    Betz, V., Rose, J.: VPR:A new packing, placement and routing tool for FPGA research. In: Luk, W., Cheung, P.Y., Glesner, M. (eds.) Field-Programmable Logic and Applications, pp. 213–222. Springer, Berlin (1997)CrossRefGoogle Scholar
  5. 5.
    Betz, V., Rose, J.: How much logic should go in an fpga logic block? IEEE Design and Test of Computers 15(1), 10–15 (1998)CrossRefGoogle Scholar
  6. 6.
    Lin, C.C., Marek-Sadowska, M., Gatlin, D.: Universal logic gate for fpga design. In: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, pp. 164–168. IEEE Computer Society Press, Los Alamitos (1994)Google Scholar
  7. 7.
    Chung, Y.Y., Bergmann, N.M.: Video compression on fpga-based custom computers. In: International Conference on Image Processing, vol. 1, pp. 361–364, October 26-29 (1997)Google Scholar
  8. 8.
    Compton, K., Hauck, S.: Reconfigurable computing: A survey of systems and software. ACM Computing Surveys (CSUR) 34(2), 171–210 (2002)CrossRefGoogle Scholar
  9. 9.
    Cong, J., Peck, J., Ding, V.: Rasp: a general logic synthesis system for sram-based fpgas. In: Proc. of ACM/SIGDA Int’l Symp. on FPGAs, pp. 137–143 (1996)Google Scholar
  10. 10.
    Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P.R., Brayton, R.K., Sangiovanni-Vincentelli, A.: SIS: A system for sequential circuit synthesis. Technical report (1992)Google Scholar
  11. 11.
    Elbirt, J., Paar, C.: An fpga implementation and performance evaluation of the serpent block chiper. In: Proc. of ACM/SIGDA Int’l Symp. on FPGAs, pp. 33–40 (2000)Google Scholar
  12. 12.
    Hartenstein, R.: A decade of reconfigurable computing: A visionary retrospective. In: Proceedings of Design, Automation and Test in Europe, pp. 642–649 (2001)Google Scholar
  13. 13.
    Hauser, J.R., Wawrzynek, J.: Garp: A mips processor with a reconfigurable coprocessor. In: Proc. of IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 12–21 (1997)Google Scholar
  14. 14.
    Heron, J., Trainor, D., Woods, R.: Image compression algorithms using re-configurable logic. In: Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers, November 2-5, vol. 1, pp. 399–403 (1997)Google Scholar
  15. 15.
    Huang, W.-J., Saxena, N., McCluskey, E.J.: Areliable lz data compressor on reconfigurable coprocessors. In: Proc. of IEEE Symp. on Field-Programmable Custom Computing Machines, April 2000, pp. 249–258 (2000)Google Scholar
  16. 16.
    Kaviani, A., Brown, S.: Hybrid fpga architecture. In: Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, Monterey, California, pp. 3–9 (1996)Google Scholar
  17. 17.
    Kimura, S., Horiyama, T., Nakanishi, M., Kajihara, H.: Folding of logic functions and its application to look up table compaction. In: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp. 694–697. ACM Press, New York (2002)Google Scholar
  18. 18.
    Kirkpatrick, S., Gelatt, J.C.D., Vecchi, M.P.: Optimization by simulated annealing. Science 220(4598), 671–680 (1983)CrossRefMathSciNetGoogle Scholar
  19. 19.
    Lemieux, G., Lewis, D.: Using sparse crossbars within lut clusters. In: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, Monterey, California, pp. 59–68 (2001)Google Scholar
  20. 20.
    Leung, K.H., Ma, K.W., Wong, W.K., Leong, P.H.W.: Fpga implementation of a microcoded elliptic curve cryptographic processor. In: Proc. of IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 68–76 (2000)Google Scholar
  21. 21.
    Ritter, J., Molitor, P.: A partitioned wavelet-based approach for image compression using fpga’s. In: Proc. of IEEE Custom Integrated Circuits Conf., May 21-24, pp. 547–550 (2000)Google Scholar
  22. 22.
    Thakur, S., Wong, D.F.: On designing ulm-based fpga logic modules. In: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, pp. 3–9. ACM Press, New York (1995)CrossRefGoogle Scholar
  23. 23.
    Trimberger, S., Duong, K., Conn, B.: Architecture issues and solutions for a high-capacity fpga. In: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, Monterey, California, pp. 3–9 (1997)Google Scholar
  24. 24.
    Villasenor, J., Mangione-Smith, W.H.: Configurable computing. Scientific AmericanGoogle Scholar
  25. 25.
    Weste, N.H., Eshraghian, K.: Principles of CMOS VLSI Design: A Systems Perspective. Addison Wesley, Reading (1995)Google Scholar
  26. 26.
    XILINX. FPGA Data Book (1996)Google Scholar
  27. 27.
    Yan, A., Cheng, R., Wilton, S.J.: On the sensitivity of fpga architectural conclusions to experimental assumptions, tools, and techniques. In: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, Monterey, California, pp. 147–156 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Fatih Kocan
    • 1
  • Jason Meyer
    • 1
  1. 1.Department of Computer Science and EngineeringSouthern Methodist UniversityDallasUSA

Personalised recommendations