A High-Density Optically Reconfigurable Gate Array Using Dynamic Method

  • Minoru Watanabe
  • Fuminori Kobayashi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


A high-density optically reconfigurable gate array (ORGA) is proposed to improve the gate density of conventional ORGAs, which are a type of Field Programmable Gate Array (FPGA). However, unlike FPGAs, an ORGA is reconfigured optically with external optical memories. A conventional ORGA has many programming elements, just as FPGAs do. One programming element consists of: a photodiode to detect an optical reconfiguration signal; a latch, a flip-flop or a bit of memory to temporarily store the reconfiguration bit; and some transistors. Among those components, the latch, flip-flop, or memory occupies a large implementation area on a typical VLSI chip; it prevents realization of a high-gate-density ORGA. This paper presents a high-density ORGA structure that eliminates latches, flip-flops, and memory using a dynamic method and a design of an ORGA-VLSI chip with four optically reconfigurable logic blocks, five optically reconfigurable switching matrices, and four optical reconfigurable I/O blocks including four I/O bits. It uses 0.35 μm 3-Metal CMOS process technology. This study also includes some experimental results.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Altera Corporation, Altera Devices,
  2. 2.
    Xilinx Inc., Xilinx Product Data Sheets,
  3. 3.
    Nakano, H., Shindo, T., Kazami, T., Motomura, M.: Development of dynamically reconfigurable processor LSI. NEC Tech. J (Japan) 56(4), 99–102 (2003)Google Scholar
  4. 4.
    Tangen, U., McCaskill, J.S.: Hardware evolution with a massively parallel dynamically reconfigurable computer: POLYP. In: Sipper, M., Mange, D., Pérez-Uribe, A. (eds.) ICES 1998. LNCS, vol. 1478, pp. 364–371. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  5. 5.
    Szymanski, T.H., Saint-Laurent, M., Tyan, V., Au, A., Supmonchai, B.: Field-programmable logic devices with optical input-output. Appl. Opt. 39, 721–732 (2000)CrossRefGoogle Scholar
  6. 6.
    Sherif, S.S., Griebel, S.K., Au, A., Hui, D., Szymanski, T.H., Hinton, H.S.: Field-programmable smart-pixel arrays: design, VLSI implementation, and applications. Appl. Opt. 38, 838–846 (1999)CrossRefGoogle Scholar
  7. 7.
    Sakr, M.F., Levitan, S.P., Giles, C.L., Chiarulli, D.M.: Reconfigurable processor employing optical channels. In: Proc. SPIE - Int. Soc. Opt. Eng., vol. 3490, pp. 564–567 (1998)Google Scholar
  8. 8.
    Watanabe, M., Ohtsubo, J.: Digital associative memory neural network with optical learning capability. Opt. Commun. 113, 31–38 (1994)CrossRefGoogle Scholar
  9. 9.
    Campenhout, J.V., Marck, H.V., Depreitere, J., Dambre, J.: Optoelectronic FPGAs. IEEE J. Sel. Top. Quantum Electron 5, 306–315 (1999)CrossRefGoogle Scholar
  10. 10.
    Mumbru, J., Panotopoulos, G., Psaltis, D., An, X., Mok, F., Ay, S., Barna, S., Fossum, E.R.: Optically Programmable Gate Array. In: Proc. SPIE - Int. Soc. Opt. Eng., vol. 4089, pp. 763–771 (2000)Google Scholar
  11. 11.
    Depreitere, J., Neefs, H., Marck, H.V., Campenhout, J.V., Baets, R., Dhoedt, B., Thienpont, H., Veretennicoff, I.: An optoelectronic 3-D field programmable gate array. In: Hartenstein, R.W., Servit, M.Z. (eds.) FPL 1994. LNCS, vol. 849, pp. 352–360. Springer, Heidelberg (1994)Google Scholar
  12. 12.
    Mumbru, J., Zhou, G., An, X., Liu, W., Panotopoulos, G., Mok, F., Psaltis, D.: Optical memory for computing and information processing. In: Proc. SPIE - Int. Soc. Opt. Eng., vol. 3804, pp. 14–24 (1999)Google Scholar
  13. 13.
    Watanabe, M., Kobayashi, F.: An optically differential reconfigurable gate array and its power consumption estimation. In: IEEE International Conference on Field-Programmable Technology, pp. 197–202 (2002)Google Scholar
  14. 14.
    Watanabe, M., Kobayashi, F.: An Optically Differential Reconfigurable Gate Array with dynamic reconfiguration circuit. In: 10th Reconfigurable Architectures Workshop, p. 188 (2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Minoru Watanabe
    • 1
  • Fuminori Kobayashi
    • 1
  1. 1.Department of Systems Innovation and InformaticsKyushu Institute of TechnologyFukuokaJapan

Personalised recommendations