Evaluating Fault Emulation on FPGA

  • Peeter Ellervee
  • Jaan Raik
  • Valentin Tihhomirov
  • Kalle Tammemäe
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to evaluate possible simulation speed possibilities, we made a feasibility study of using reconfigurable hardware by emulating circuit under analysis together with fault insertion structures on FPGA. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms.


Test Vector Fault Injection Binary Decision Diagram Linear Feedback Shift Register Fault Simulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Peeter Ellervee
    • 1
  • Jaan Raik
    • 1
  • Valentin Tihhomirov
    • 1
  • Kalle Tammemäe
    • 1
  1. 1.Department of Computer EngineeringTallinn University of TechnologyTallinnEstonia

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