Advertisement

Compact Buffered Routing Architecture

  • A. Lodi
  • R. Giansante
  • C. Chiesa
  • L. Ciccarelli
  • F. Campi
  • M. Toma
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

In this paper we propose a new routing architecture, based on a new switch called T-switch, which we implement in two different versions. Our approach is based on a modified disjoint topology in order to reduce the number of buffers required and on the introduction of a decoding stage between configuration memories and the switch to reduce the number of SRAM cells. This solution is particularly suitable for multi-context arrays, where configuration memory cells need to be replicated as many times as the number of contexts.

The buffered switch proposed has been implemented in two different gate array architectures, in order to evaluate its effectiveness. The results show that the T-switch routing architecture reduces the device area occupation up to 29% in a 4-context array. We also show that the critical path delay is reduced, while routability is substantially unaffected.

Keywords

Logic Block Area Occupation SRAM Cell Device Area Critical Path Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    DeHon, A.: DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California, April 1994, pp. 31–39 (1994)Google Scholar
  2. 2.
    Trimberger, S., Carberry, D., Jhonson, A., Wong, J.: A Time Multiplexed FPGA. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California, April 1997, pp. 34–40 (1997)Google Scholar
  3. 3.
    Sheng, M., Rose, J.: Mixing buffers and pass transistors in FPGA routing architectures. In: ACM/SIGDA International Symposium on FPGAs, pp. 75–84 (February 2001)Google Scholar
  4. 4.
    Lemieux, G., Lewis, D.: Circuit Design of Routing Switches. In: ACM/SIGDA International Symposium on FPGAs (February 2002)Google Scholar
  5. 5.
    DeHon, A.: Entropy, Counting, and Programmable Interconnect. In: ACM/SIGDA International Symposium on FPGAs (February 1996)Google Scholar
  6. 6.
    Lodi, A., Ciccarelli, L., Cappelli, A., Campi, F.: M, Toma. Decoder-based interconnect structure for multi-context FPGAs. Electronic Letters 38, 362–364 (2003)CrossRefGoogle Scholar
  7. 7.
    Betz, V., Rose, J.: VPR: A New Packing, Placement, and Routing Tool for FPGA Research. In: International Workshop on Field Programmable Logic and Applications (September 1997)Google Scholar
  8. 8.
    Lodi, A., Toma, M., Campi, F., Cappelli, A., Canegallo, R., Guerrieri, R.: A Pipelined Configurable Gate Array for Embedded Processors. In: Proceedings of the 11th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2003, pp. 21–30 (2003)Google Scholar
  9. 9.
    Mucci, C., Chiesa, C., Lodi, A., Toma, M., Campi, F.: A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture. In: International Symposium on System-on-Chip, Tampere, Finland (2003)Google Scholar
  10. 10.
    Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P.R., Brayton, R.K., Sangiovanni-Vincentelli, A.: SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41 (1992)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • A. Lodi
    • 1
  • R. Giansante
    • 1
  • C. Chiesa
    • 1
  • L. Ciccarelli
    • 1
  • F. Campi
    • 1
  • M. Toma
    • 2
  1. 1.ARCES University of BolognaBologna
  2. 2.STMicroelectronics, NVM-DP, CR&DAgrate BrianzaItaly

Personalised recommendations