Compact Buffered Routing Architecture
In this paper we propose a new routing architecture, based on a new switch called T-switch, which we implement in two different versions. Our approach is based on a modified disjoint topology in order to reduce the number of buffers required and on the introduction of a decoding stage between configuration memories and the switch to reduce the number of SRAM cells. This solution is particularly suitable for multi-context arrays, where configuration memory cells need to be replicated as many times as the number of contexts.
The buffered switch proposed has been implemented in two different gate array architectures, in order to evaluate its effectiveness. The results show that the T-switch routing architecture reduces the device area occupation up to 29% in a 4-context array. We also show that the critical path delay is reduced, while routability is substantially unaffected.
KeywordsLogic Block Area Occupation SRAM Cell Device Area Critical Path Delay
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