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Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation

  • Chun Te Ewe
  • Peter Y. K. Cheung
  • George A. Constantinides
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

This paper presents a new data representation known as Dual FiXed-point (DFX), which employs a single bit exponent to select two different fixed-point scalings. DFX provides a compromise between conventional fixed-point and floating-point representations. It has the implementation complexity similar to that of a fixed-point system together with the improved dynamic range offered by a floating-point system. The benefit of using DFX over both fixed-point and floating-point is demonstrated with an IIR filter implementation on a Xilinx Virtex II FPGA.

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References

  1. 1.
    Constantinides, G.A., Cheung, P.Y.K., Luk, W.: Wordlength optimization for linear digital signal processing. IEEE Transactions on CAD of Integrated Circuits and Systems 22, 1432–1442 (2003)CrossRefGoogle Scholar
  2. 2.
    Gaffar, A.A., Luk, W., Cheung, P.Y.K., Shirazi, N.: Customising floating-point designs. In: IEEE Symposium on Field-Programmable Custom Computing Machines (2002)Google Scholar
  3. 3.
    Inacio, C., Ombres, D.: The DSP decision: fixed point or floating? IEEE Spectrum 33, 72–74 (1996)CrossRefGoogle Scholar
  4. 4.
    Oppenheim, A.V., Weistein, C.J.: Effects of finite register length in digital filtering and the fast fourier transform. Proceedings of the IEEE 60, 957–976 (1972)CrossRefGoogle Scholar
  5. 5.
    Horrocks, D.H., Bull, D.R.: A floating-point FIR filter with reduced exponent dynamic range. In: IEEE International Symposium on Circuits and Systems (1992)Google Scholar
  6. 6.
    Wust, H., Kasper, K., Reininger, H.: Hybrid number representation for the FPGA-realization of a versatile neuro-processor. In: Euromicro Conference (1998)Google Scholar
  7. 7.
    Oppenheim, A.V.: Realisation of digital filters using block-floating-point arithmetic. IEEE Transaction on Audio and Electroacoustics 18, 130–136 (1970)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Chun Te Ewe
    • 1
  • Peter Y. K. Cheung
    • 1
  • George A. Constantinides
    • 1
  1. 1.Department of Electrical & Electronic EngineeringImperial CollegeLondonEngland

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