1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 199 - 199

2. Testability and test generation for majority voting fault-tolerant circuits

   • Charles E. Stroud
   • Ahmed E. Barbour

   Fault-tolerant and Testable Design Pages: 201 - 214

3. On the testability of array structures for FFT computation

   • Chao Feng
   • Jon C. Muzio
   • Fabrizio Lombardi

   Fault-tolerant and Testable Design Pages: 215 - 224

4. A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

   • Zaifu Zhang
   • Robert D. Mcleod
   • Witold Pedrycz

   Switch-level Testing Pages: 225 - 235

5. On the generation of test patterns for multiple faults

   • El Mostapha Aboulhamid
   • Younès Karkouri
   • Eduard Cerny

   Test Generation Pages: 237 - 253

6. A fault simulation method: Parallel pattern critical path tracing

   • Byung S. So
   • Charles R. Kime

   Fault-simulation Pages: 255 - 265

7. Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

   • E. S. Sogomonyan
   • M. Goessel

   Built-in Self Test Pages: 267 - 281

8. Testing of multi-output circuits by means of signature analyzer

   • Ye. L. Stolov

   Jetta Letters Pages: 283 - 283

9. The optimistic update theorem for path delay testing in sequential circuits

   • Soumitra Bose
   • Prathima Agrawal
   • Vishwani D. Agrawal

   Jetta Letters Pages: 285 - 290