Abstract
In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.
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Zhang, Z., Mcleod, R.D. & Pedrycz, W. A neural network algorithm for testing stuck-open faults in CMOS combinational circuits. J Electron Test 4, 225–235 (1993). https://doi.org/10.1007/BF00971972
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DOI: https://doi.org/10.1007/BF00971972