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On the generation of test patterns for multiple faults

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Abstract

This article presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.

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Authors and Affiliations

  1. Dep. d'informatique et de recherche opérationnelle, Université de Montréal, C.P. 6128, Succ. “A”, H3C-3J7, Montréal, (Québec), Canada

    El Mostapha Aboulhamid, Younès Karkouri & Eduard Cerny

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  1. El Mostapha Aboulhamid
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  2. Younès Karkouri
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  3. Eduard Cerny
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Aboulhamid, E.M., Karkouri, Y. & Cerny, E. On the generation of test patterns for multiple faults. J Electron Test 4, 237–253 (1993). https://doi.org/10.1007/BF00971973

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  • DOI: https://doi.org/10.1007/BF00971973

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