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Journal of Electronic Testing

, Volume 4, Issue 3, pp 201–214 | Cite as

Testability and test generation for majority voting fault-tolerant circuits

  • Charles E. Stroud
  • Ahmed E. Barbour
Fault-tolerant and Testable Design

Abstract

The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software.

Key words

Design for testability fault-tolerance majority voting circuits multiple stuck-at faults test pattern generation 

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Copyright information

© Kluwer Academic Publishers 1993

Authors and Affiliations

  • Charles E. Stroud
    • 1
  • Ahmed E. Barbour
    • 2
  1. 1.AT&T Bell LaboratoriesNaperville
  2. 2.Dept. of Mathematics & Computer ScienceGeorgia Southern UniversityStatesboro

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