An optimal methodology for synthesis of DSP multichip architectures Catherine H. Gebotys OriginalPaper 01 October 1995 Pages: 9 - 19
Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems Sati BanerjeePaul M. ChauRonald D. Fellman OriginalPaper 01 October 1995 Pages: 21 - 34
A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs Hyeong -Kyo KimThomas P. Barnwell III OriginalPaper 01 October 1995 Pages: 35 - 50
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques Mirjam SchönfeldJens FranzenAndreas Münzner OriginalPaper 01 October 1995 Pages: 51 - 74
Resource-constrained loop list scheduler for DSP algorithms Ching -Yi WangKeshab K. Parhi OriginalPaper 01 October 1995 Pages: 75 - 96
Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures Marc PauwelsGert GoossensHugo De Man OriginalPaper 01 October 1995 Pages: 97 - 112
Converting affine recurrence equations to quasi-uniform recurrence equations Yoav YaacobyPeter Cappello OriginalPaper 01 October 1995 Pages: 113 - 131
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays Yin -Tsung HwangYu Hen Hu OriginalPaper 01 October 1995 Pages: 133 - 150
Design techniques for fault-tolerant systolic arrays M. O. EsonuA. J. Al-KhaliliD. Al-Khalili OriginalPaper 01 October 1995 Pages: 151 - 168
A special purpose formal verifier for systolic designs in DSP applications Nam Ling OriginalPaper 01 October 1995 Pages: 169 - 187