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Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures

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Abstract

Multiple precision arithmetic is very useful to optimally trade off area and time when implementing real-time signal processing algorithms on application specific architectures. A wide range of area-time tradeoffs is possible in multiple precision, with the degree of multi-precision as a parameter. To cope with this complex optimisation problem, there is definitely a need for good models and support by synthesis tools. This paper describes how multiple precision arithmetic has been formalised and implemented in formal software procedures within theCathedral-2nd high-level synthesis environment, developed at IMEC. The use of multiple precision arithmetic is illustrated by means of a design of an industrial application.

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Author notes

  1. Marc Pauwels

    Present address: Antwerp Bionic Systems, Drie Eikenstraat 661, B-2650, Edegem, Belgium

Authors and Affiliations

  1. IMEC, Kapeldreef 75, B-3001, Leuven, Belgium

    Marc Pauwels, Gert Goossens, Francky Catthoor & Hugo De Man (Professor)

  2. Katholieke Universiteit Leuven, Belgium

    Hugo De Man (Professor)

Authors
  1. Marc Pauwels
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  2. Gert Goossens
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  3. Francky Catthoor
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  4. Hugo De Man
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Pauwels, M., Goossens, G., Catthoor, F. et al. Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures. Journal of VLSI Signal Processing 11, 97–112 (1995). https://doi.org/10.1007/BF02106825

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