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Resource-constrained loop list scheduler for DSP algorithms

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Abstract

We present a new algorithm for resource-constrained scheduling for digital signal processing (DSP) applications when the number of processors is fixed and the objective is to obtain a schedule with the minimum iteration period. This type of scheduling is best suited for moderate speed applications where conservation of area and power is more important than speed. We define and make use of newgraph dependent constraints to obtain a lower bound estimate on the iteration period for any data-flow graph. By satisfying these constraints before performing the scheduling task, we can restrict the design space and can generate valid schedules in less time than previously reported. The graph dependent constraints provide a more accurate lower bound estimate on the iteration period than previously published results. This new scheduling algorithm exploits the iterative nature of DSP algorithms and uses aniterative-loop based scheduling approach. This resource scheduling algorithm has been incorporated in the Minnesota ARchitecture Synthesis (MARS) system. Our approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining to generate optimal and near optimal schedules.

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Authors and Affiliations

  1. Department of Electrical Engineering, University of Minnesota, 55455, Minneapolis, Minnesota

    Ching -Yi Wang & Keshab K. Parhi

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  1. Ching -Yi Wang
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  2. Keshab K. Parhi
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Additional information

This research was supported by the Advanced Research Projects Agency under grant number F33615-93-C-1309 and the office of Naval Research under contract number N00014-91-J-1008.

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Wang, C.Y., Parhi, K.K. Resource-constrained loop list scheduler for DSP algorithms. Journal of VLSI Signal Processing 11, 75–96 (1995). https://doi.org/10.1007/BF02106824

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