Abstract
This paper describes a design synthesis environment which can generate an efficient VLSI layout from a recursive DSP algorithm specified by a graph. The design synthesis environment is divided into three parts: optimal schedule generation, circuit synthesis, and VLSI layout generation (silicon compilation). The scheduler first computes optimality conditions for a given input algorithm and then finds a schedule which satisfies the optimality conditions. We have employed a cyclo-static optimal multiprocessor compiler as a scheduler. The circuit synthesis component translates the optimal schedule into a structural specification, including the control structures, for an circuit realization. In the final part, a VLSI layout is generated from the structural specification. We have chosen the LAGER system for the silicon compilation. This paper illustrates the design synthesis process with complete details of a simple, complete example, a second order Direct Form II IIR filter.
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This work was supported in part under the Joint Services Electronics Program Contract # DAAL-03-90-C-0004.
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Kim, H.K., Barnwell, T.P. A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs. Journal of VLSI Signal Processing 11, 35–50 (1995). https://doi.org/10.1007/BF02106822
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DOI: https://doi.org/10.1007/BF02106822