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An optimal methodology for synthesis of DSP multichip architectures

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Abstract

An optimization approach to the synthesis of multichip DSP architectures is presented in this paper. This research is important for Industry since it is well known that these early design decisions have a significant impact on the final VLSI implementation. A mathematical programming approach to simultaneously scheduling, partitioning (into multiple chips) and allocating minimum hardware (functional units on each chip) for the DSP application is formulated. Throughput, input/output timing, and latency constraints are supported along with interchip communication delays. By using polyhedral theory, the optimal solution to the integer programming problem can be obtained in fast cpu times. Results show that we can synthesize optimal two-chip, three-chip and four-chip architectures for a realistic Industrial DSP application in reasonable cpu times. This research breaks new ground by simultaneously partitioning, scheduling and allocating multichip DSP architectures with optimal area in fast cpu times.

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  1. Department of Electrical and Computer Engineering, University of Waterloo, N2L 3G1, Waterloo, Ontario

    Catherine H. Gebotys

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  1. Catherine H. Gebotys
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Gebotys, C.H. An optimal methodology for synthesis of DSP multichip architectures. Journal of VLSI Signal Processing 11, 9–19 (1995). https://doi.org/10.1007/BF02106820

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  • DOI: https://doi.org/10.1007/BF02106820

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