Abstract
The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability.
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Schönfeld, M., Franzen, J., Schwiegershausen, M. et al. The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques. Journal of VLSI Signal Processing 11, 51–74 (1995). https://doi.org/10.1007/BF02106823
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DOI: https://doi.org/10.1007/BF02106823