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Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems

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Abstract

A methodology for the hierarchical partitioning and mapping of digital signal processing (DSP) tasks to heterogeneous local cluster based network of very large scale integration (VLSI) processors is presented. The goal is to achieve rapid prototyping of VLSI DSP systems. The high level partitioning issues of DSP task graphs and the proposed metrics to guide the partitioning process are described in this paper. Partitioning tominimize power inefficiency in the DSP system is one important metric addressed by this work, since low power signal processing is paramount to new portable and high density multi-chip module (MCM) DSP systems. The application of theRatio Cut Partitioning approach to DSP graphs is explained. We illustrate our results with examples and show how the final partitions vary depending upon the target architecture to meet rapid prototyping requirements. We compare our approach with known techniques and show that it works much better for our target applications.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of California, 92093-0407, San Diego, La Jolla, CA

    Sati Banerjee, Paul M. Chau & Ronald D. Fellman

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  1. Sati Banerjee
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  2. Paul M. Chau
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  3. Ronald D. Fellman
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Banerjee, S., Chau, P.M. & Fellman, R.D. Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems. Journal of VLSI Signal Processing 11, 21–34 (1995). https://doi.org/10.1007/BF02106821

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  • DOI: https://doi.org/10.1007/BF02106821

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