Abstract
This paper addresses the partitioning and scheduling problems in mapping multi-stage regular iterative algorithms onto fixed size distributed memory processor arrays. We first propose a versatile partitioning model which provides a unified framework to integrate various partitioning schemes such as “locally sequential globally parallel”, “locally parallel globally sequential” and “multi-projection”. To alleviate the run time data migration overhead—a crucial problem to the mapping of multi-stage algorithms, we further relax the widely adopted atomic partitioning constraint in our model such that a more flexible partitioning scheme can be achieved. Based on this unified partitioning model, a novel hierarchical scheduling scheme which applies separate schedules at different processor hierarchies is then developed. The scheduling problem is then formulated into a set of ILP problem and solved by the existing software package for optimal solutions. Examples indicate that our partitioning model is a superset of the existing schemes and the proposed hierarchical scheduling scheme can outperform the conventional one-level linear schedule.
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Hwang, Y.T., Hu, Y.H. A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays. Journal of VLSI Signal Processing 11, 133–150 (1995). https://doi.org/10.1007/BF02106827
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DOI: https://doi.org/10.1007/BF02106827