This volume contains the proceedings of the 4th International Workshop on Field-Programmable Logic and Applications (FPL '94), held in Prague, Czech Republic in September 1994. The growing importance of field-programmable devices is substantiated by the remarkably high number of 116 submissions for FPL '94; from them, the revised versions of 40 full papers and 24 high-quality poster presentations were accepted for inclusion in this volume. Among the topics treated are: testing, layout, synthesis tools, compilation research and CAD, trade-offs and experience, innovations and smart applications, FPGA-based computer architectures, high-level design, prototyping and ASIC emulators, commercial devices, new tools, CCMs and HW/SW co-design, modelers, educational experience, and novel architectures.

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Table of contents (63 papers)

Front Matter

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Fault modeling and test generation for FPGAs
- Michael Hermann, Wolfgang Hoffmann
Pages 1-10
A test methodology applied to Cellular logic Programmable Gate Arrays
- Ricardo de O. Duarte, Mihaîl Nicolaidis
Pages 11-22
Integrated layout synthesis for FPGA's
- Michal Z. Servít, Zdeněk Muzikář
Pages 23-33
Influence of logic block layout architecture on FPGA performance
- M. Robert, L. Torres, F. Moraes, D. Auvergne
Pages 34-44
A global routing heuristic for FPGAs based on mean field annealing
- Ismail Haritaoğlu, Cevdet Aykanat
Pages 45-56
Power dissipation driven FPGA place and route under delay constraints
- Kaushik Roy, Sharat Prasad
Pages 57-65
FPGA technology mapping for power minimization
- Amir H. Farrahi, Majid Sarrafzadeh
Pages 66-77
Specification and synthesis of complex arithmetic operators for FPGAs
- Hans-Juergen Brand, Dietmar Mueller, Wolfgang Rosenstiel
Pages 78-88
A speed-up technique for synchronous circuits realized as LUT-based FPGAs
- Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta
Pages 89-92
An efficient technique for mapping RTL structures onto FPGAs
- A. R. Naseer, M. Balakrishnan, Anshul Kumar
Pages 99-110
A testbench design method suitable for FPGA-based prototyping of reactive systems
- Volker Hamann
Pages 111-113
Using consensusless covers for fast operating on Boolean functions
- Eugene Goldberg, Ludmila Krasilnikova
Pages 114-116
Formal verification of timing rules in design specifications
- Tibor Bartos, Norbert Fristacky
Pages 117-119
Optimized synthesis of self-testable finite state machines (FSM) using BIST-PST structures in Altera structures
- Andrzej Hlawiczka, IEEE, Jacek Binda
Pages 120-122
A high-speed rotation processor
- Jan Lichtermann, Günter Neustädter
Pages 123-125
The MD5 message-digest algorithm in the XILINX FPGA
- P. Gramata, P. Trebatický, E. Gramatová
Pages 126-128
A reprogrammable processor for fractal image compression
- Barry Fagin, Pichet Chintrakulchai
Pages 129-131
Implementing GCD systolic Arrays on FPGA
- Tudor Jebelean
Pages 132-134
Formal CAD techniques for safety-critical FPGA design and deployment in embedded subsystems
- R. B. Hughes, G. Musgrave
Pages 135-137

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Field-Programmable Logic Architectures, Synthesis and Applications

Bibliographic Information

Book Title: Field-Programmable Logic: Architectures, Synthesis and Applications
Book Subtitle: 4th International Workshop on Field-Programmable Logic and Applications, FPL'94, Prague, Czech Republic, September 7 - 9, 1994. Proceedings
Editors: Reiner W. Hartenstein, Michal Z. Servít
Series Title: Lecture Notes in Computer Science
DOI: https://doi.org/10.1007/3-540-58419-6
Publisher: Springer Berlin, Heidelberg
eBook Packages: Springer Book Archive
Copyright Information: Springer-Verlag Berlin Heidelberg 1994
Softcover ISBN: 978-3-540-58419-3Published: 24 August 1994
eBook ISBN: 978-3-540-48783-8Published: 05 July 2005
Series ISSN: 0302-9743
Series E-ISSN: 1611-3349
Edition Number: 1
Number of Pages: XIII, 439
Topics: Computer System Implementation, Software Engineering/Programming and Operating Systems, Logic Design, Electronics and Microelectronics, Instrumentation, Computer-Aided Engineering (CAD, CAE) and Design

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Table of contents (63 papers)

Front Matter

Fault modeling and test generation for FPGAs

A test methodology applied to Cellular logic Programmable Gate Arrays

Integrated layout synthesis for FPGA's

Influence of logic block layout architecture on FPGA performance

A global routing heuristic for FPGAs based on mean field annealing

Power dissipation driven FPGA place and route under delay constraints

FPGA technology mapping for power minimization

Specification and synthesis of complex arithmetic operators for FPGAs

A speed-up technique for synchronous circuits realized as LUT-based FPGAs

An efficient technique for mapping RTL structures onto FPGAs

A testbench design method suitable for FPGA-based prototyping of reactive systems

Using consensusless covers for fast operating on Boolean functions

Formal verification of timing rules in design specifications

Optimized synthesis of self-testable finite state machines (FSM) using BIST-PST structures in Altera structures

A high-speed rotation processor

The MD5 message-digest algorithm in the XILINX FPGA

A reprogrammable processor for fractal image compression

Implementing GCD systolic Arrays on FPGA

Formal CAD techniques for safety-critical FPGA design and deployment in embedded subsystems

Other volumes