Fault modeling and test generation for FPGAs

  • Michael Hermann
  • Wolfgang Hoffmann
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)


This paper derives a fault model for one-time programmable FPGAs from the general functional fault model and an algorithm to perform test generation according to this model. The new model is characterized by the abstraction of functional faults from a set of possible implementations of a circuit. In contrast to other functional-level test generation procedures a fault coverage of 100% can be achieved regardless of the final implementation of the circuit.


Boolean Function Logic Module Test Generation Field Programmable Gate Array Function Identification 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Thirumalai Sridhar and John P. Hayes: “A Functional Approach to Testing Bit-Sliced Microprocessors”.-In: IEEE Transactions on Computers, Vol. 30, No. 8. (1981) pp. 563–572Google Scholar
  2. 2.
    Utpal J. Dave and Janak H. Patel: “A Functional-Level Test Generation Methodology using Two-Level Representations”.-In: 26th ACM/IEEE Design Automation Conference DAC. (1989) pp. 722–725Google Scholar
  3. 3.
    Chien-Hung Chao, F. Gail Gray: “Micro-Operation Perturbations in Chip Level Fault Modeling”.-In:25th ACM/IEEE Design Automation Conference DAC. (1988) pp. 579–582Google Scholar
  4. 4.
    Brian T. Murray and John P. Hayes: “Hierarchical Test Generation Using Precomputed Tests for Modules”.-In:IEEE International Test Conference. (1988) pp. 221–229Google Scholar
  5. 5.
    A. Zemva and F. Brglez and K. Kozminski: “Functionality Test and Don't Care Synthesis in FPGA ICs”.-In:MCNC, Research Triangle Park, NC, Technical Report TR93-04. (1993)Google Scholar
  6. 6.
    Khalet A. El-Ayat, Abbas El Gamal, Richard Guo et al.: “A CMOS Electrically Configurable Gate Array”.-In:IEEE Journal of Solid State Circuits, Vol. 24, No. 3. (1989) pp. 752–761Google Scholar
  7. 7.
    M. H. Schulz, E. Trischler and T. M. Sarfert: “SOCRATES: A Highly Efficient ATPG System”.-In:IEEE Transactions on Computer-Aided Design Vol. 7, No. 1. (1988) pp. 126–137Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Michael Hermann
    • 1
  • Wolfgang Hoffmann
    • 1
  1. 1.Institute of Electronic Design Automation, Department of Electrical EngineeringTechnical University of MunichMunichGermany

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