Implementing GCD systolic Arrays on FPGA
We implement on Field Programmable Gate Arrays from Amtel (old CLi) three systolic algorithms for the computation of greatest common divisor of integers. The experiments show that elimination of global broadcasting significantly reduces both area and time consumption. We eliminate broadcasting by using a novel technique which is more suitable to arithmetic algorithms than Leiserson conversion lemma.
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- BrKu85.R. P. Brent, H. T. Kung, A systolic algorithm for integer GCD computation, 7th IEEE Symp. on Computer Arithmetic.Google Scholar
- Guyo91.A. Guyot, OCAPI: Architecture of a VLSI coprocessor for the GCD and extended GCD of large numbers, 10th IEEE Symposium on Computer Arithmetic.Google Scholar
- Jebe93.T. Jebelean, Systolic normalization of rational numbers, ASAP'93.Google Scholar
- Jebe94.T. Jebelean, Systolic algorithms for long integer GCD computation, Conpar94.Google Scholar
- Leis82.C. E. Leiserson, Area-efficient VLSI computation, PhD Thesis, Carnegie Mellon University, MIT Press, 1982.Google Scholar
- YuZh86.D. Y. Y. Yun, C. N. Zhang, A fast carry-free algorithm and hardware design for extended integer GCD computation, ACM SYMSAC'86.Google Scholar