A speed-up technique for synchronous circuits realized as LUT-based FPGAs

  • Toshiaki Miyazaki
  • Hiroshi Nakada
  • Akihiro Tsutsui
  • Kazuhisa Yamada
  • Naohisa Ohta
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)


This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration except for latch location. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., re-mapping, re-placement and re-routing, are unnecessary to improve circuit performance.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Toshiaki Miyazaki
    • 1
  • Hiroshi Nakada
    • 1
  • Akihiro Tsutsui
    • 1
  • Kazuhisa Yamada
    • 1
  • Naohisa Ohta
    • 1
  1. 1.NTT Transmission Systems LaboratoriesKanagawaJapan

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