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A test methodology applied to Cellular logic Programmable Gate Arrays

  • Ricardo de O. Duarte
  • Mihaîl Nicolaidis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)

Abstract

This paper describes an approach for testing a class of programmable logic devices called Cellular Programmable Gate Arrays. The flexibility in the selection of logic functions and the high number of interconnections in this class of devices turns test a complex task. It has led to the proposition of an efficient test procedure based on some function properties. The regularity of the procedure permits that all logic cells in the device can be tested completly for functional faults at the same time, whenever is possible. It provides a reduced number of reprogramming times during test mode and a possibility of testing more devices in a defined period of time.

Keywords

Greedy Algorithm Field Programmable Gate Array Sequential Function Functional Fault Programmable Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Algotronix Ltd.: “CAL1024 — Preliminary Data Sheet”. Algotronix Ltd.-Edinburgh, U.K., 1988.Google Scholar
  2. 2.
    Concurrent Logic Inc.: “CLI6000 Series Field Programmable Gate Arrays”. Preliminary Information, Dec. 1991-rev.:1.3.Google Scholar
  3. 3.
    S. Hauck, G. Boriello, S. Burns and C. Ebeling: “Montage: An FPGA for Synchronous and Asynchronous Circuits”. 2nd. International Workshop on Field Programmable Logic and Applications, Vienna — Austria. Springer pp. 44–51, 1992.Google Scholar
  4. 4.
    J.P. Gray and T.A. Kean: “Configurable Hardware: A New Paradigm for Computation”. Proceedings of Decennial Caltech Conference on VLSI, Pasadena, CA. March 1989.Google Scholar
  5. 5.
    C. Jordan and W.P. Marnane: “Incoming Inspection of FPGA's”. in European Test Conference. pp. 371–376, 1993.Google Scholar
  6. 6.
    W.P. Marnane and W.R. Moore: “Testing Regular Arrays: The Boundary Problem”. European Test Conference, pp. 304–311, 1989.Google Scholar
  7. 7.
    Michael Demjanenko and Shambhu J. Upadhyaya: “Dynamic Techniques for Yield Enhancement of Field Programmable Logic Arrays”. IEEE International Test Conference. pp. 485–491, 1988.Google Scholar
  8. 8.
    Hideo Fujiwara: “Logic Testing and Design for Testability”. Computer System series, the MIT Press, 1986.Google Scholar
  9. 9.
    Robert Sedgwick: “Algorithms”. Addison-Wesley Publishing Company Inc. 1988.Google Scholar
  10. 10.
    Ricardo O. Duarte, Edil S. T. Fernades, A. C. Mesquita, A.L.V. Azevedo: “Configurable Cells: Towards Dynamics Architectures”. Microprocessing and Microprogramming, The EUROMICRO Journal-North Holland Editor, vol. 38 N∘ 1–5 pp. 221–224, February 1993.Google Scholar
  11. 11.
    Kean, T.: “Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation”. Ph.D. Thesis, University of Edinburgh, Dept. of Computer Science, 1989.Google Scholar
  12. 12.
    J.Rose, A. El Gamal, Sangiovanni-Vicentelli: “Architecture of Field-Programmable Gate Arrays”. Proceedings of IEEE, vol. 81, n∘ 7-July 1993.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Ricardo de O. Duarte
    • 1
  • Mihaîl Nicolaidis
    • 1
  1. 1.Reliable Integrated Systems Group IMAG/TIMAGrenoble CedexFrance

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