Integrated layout synthesis for FPGA's
A new approach to the layout of FPGA's is presented. This approach integrates replacement and global routing into a compound task. An iterative algorithm solving the compound task is proposed. This algorithm takes into account restrictions imposed by the rigid carrier structure of FPGA's as well as the timing requirements dictated by the clocking scheme. A complex cost function is employed to control the iterative process in order to satisfy all restrictions and to optimize the circuit layout efficiency and performance.
Unable to display preview. Download preview PDF.
- 1.Brown, S.D., Francis, R.J., Rose, J., Vranesic, Z.G.: Field-Programmable Gate Arrays. Kluwer, Boston, 1992.Google Scholar
- 2.Lengauer, T.: Combinatorial Algorithms for Integrated Circuit Layout. Wiley-Teubner, Stuttgart-New York, 1990.Google Scholar
- 3.Muzikář, Z., Schmidt, J.: Experiments with Placement Algorithms on Gate Arrays. APK'92: Proc. of Design Automation Conference, Kaunas, 1992, pp. 86–91.Google Scholar
- 4.Sapatnekar, S.S., Kang, S.M.: Design Automation for Timing-Driven Layout Synthesis. Kluwer, Boston, 1992.Google Scholar
- 5.Servít, M.: Iterative Approach to Global Routing. J. Semicustom ICs, Vol.8, No.3, 1991, pp. 18–24.Google Scholar
- 6.Servít, M.: Algorithmic Problems of VLSI Layout. CTU Workshop'92, Praha 1992, pp. 91–92.Google Scholar
- 7.Sherwani, N.A.: Algorithms for VLSI Physical Design Automation. Kluwer, Boston, 1993.Google Scholar
- 8.Tomkevičius, A., Muzikář, Z., Servít, M.: Integrated Approach to Placement and Global Routing in Gate Arrays. Research Report DC-94-04, Czech Technical University, Dept. of Computers, Prague, 1994.Google Scholar
- 9.XILINX — The Programmable Gate Array Data Book. San Jose, 1992.Google Scholar