Integrated layout synthesis for FPGA's

  • Michal Z. Servít
  • Zdeněk Muzikář
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)


A new approach to the layout of FPGA's is presented. This approach integrates replacement and global routing into a compound task. An iterative algorithm solving the compound task is proposed. This algorithm takes into account restrictions imposed by the rigid carrier structure of FPGA's as well as the timing requirements dictated by the clocking scheme. A complex cost function is employed to control the iterative process in order to satisfy all restrictions and to optimize the circuit layout efficiency and performance.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Michal Z. Servít
    • 1
  • Zdeněk Muzikář
    • 1
  1. 1.Dept. of ComputersCzech Technical UniversityPraha 2Czech Republic

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