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Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications

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Abstract

A low-power, high-speed two-stage dynamic latch comparator suitable for high-resolution analog-to-digital converters (ADCs) is described and implemented in this work using 22 nm FinFET technology. The purpose of this research is to apply the FinFET device in low-power, high-speed analogue and mixed-signal circuits. Today, in the sub-50 nm realm, FinFETs outperform planar MOSFETs in terms of performance. In addition to a high voltage gain, other benefits include better channel control, reduced short-channel effects, low leakage current at the output, and a low output conductance. The suggested dynamic latched comparator makes use of both CMOS and FinFET technology components. By studying the device properties, the analogue performance metrics of FinFET are compared to bulk CMOS. Most dynamic comparators are able to function at fast speeds for input referred noise levels that are sufficiently high. This is because high-resolution ADCs do not benefit from the pre-amplifier's limited gain. This shortcoming is addressed by way of a pre-amplifier based on a cascode structure. The proposed comparator architectures improve the pre- amplifier differential gain and minimize input referred noise. In addition, a tranconductance enhanced latch stage is used. Using 0.8 V as a supply voltage and 1 GHz clock frequency, the suggested comparator has a delay as low as 50.42 ps, input referred noise of 190 µv and an input offset voltage of 5.2 mV with a power consumption of 7.67 µW and with a low power delay product (PDP) of 0.382 fJ. The FinFET based dynamic latch comparator has 20.6%, of delay and 12.5% power dissipation improvement than bulk CMOS based dynamic latch comparator and also better PDP than conventional double tail pre-amplifier based dynamic comparators. The proposed circuit's active area is 5.93 µm × 2.85 µm.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Warangal, India

    K. Sarangam

  2. Department of ECE, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, Telangana, India

    Aruru Sai Kumar

  3. Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu, India

    B. Naresh Kumar Reddy

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Sarangam, K., Kumar, A.S. & Reddy, B.N.K. Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications. Trans. Electr. Electron. Mater. 25, 218–231 (2024). https://doi.org/10.1007/s42341-023-00503-2

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