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Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

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Abstract

In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12 nm with Contact poly pitch (CPP) of 48 nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10−16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 1011 has been achieved. The device exhibits a high transconductance of 3.022 × 10−5 S at the gate to source voltage of 1 V. The radiation effect of an alpha particle at different energies on NS-TFET is investigated. The injection causes drain current fluctuation for a short span and the result can serve as a guideline for designing of a robust circuit. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

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Acknowledgements

We thank the Group, department of Electronics Technology, Guru Nanak Dev University, Amritsar for their interest in this work and useful comments to draft the final form of the paper. The support of CADRE Design Systems is gratefully acknowledged. We would like to thank Guru Nanak Dev University, Amritsar and Cadre Design Systems for lab facilities and research environment to carry out this work.

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Authors and Affiliations

  1. Electronics Technology Department, GNDU, Amritsar, Punjab, India

    Garima Jain, Ravinder Singh Sawhney & Ravinder Kumar

  2. TCAD expert at Cadre Design Systems, Delhi, India

    Amit Saini

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  1. Garima Jain
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  2. Ravinder Singh Sawhney
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  3. Ravinder Kumar
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  4. Amit Saini
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Contributions

All authors contributed to the design and simulation. Material preparation, data collection and analysis were performed by Garima Jain, Dr. Ravinder Singh Sawhney, Dr. Ravinder Kumar and Amit Saini. The first draft of the manuscript was written by Garima Jain and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

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Correspondence to Garima Jain.

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This study was ap-proved by the university research ethics committee. All procedures per-formed in this study follow the ethical standards of the institutional and research committee.

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Jain, G., Sawhney, R.S., Kumar, R. et al. Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing. Silicon 14, 5067–5074 (2022). https://doi.org/10.1007/s12633-021-01302-1

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