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Analysis of subthreshold SOI FinFET based two stage OTA for low power

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Abstract

In this paper, subthreshold design and analysis of Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) based two stage Operational Transconductance Amplifier (OTA) is presented for low power and low supply voltage in nanometre regime. The OTA design optimization is achieved by \(g_{m}/I_{D}\) methodology which helps to determine the device aspect ratios. Compactness is achieved by using nanometre FinFET technology. The OTA design is simulated using 30 nm SOI FinFET Berkeley Short-channel IGFET Common Multi-gate (BSIM-CMG) model, with bias current and supply voltage of 20 nA and \(\pm 0.5 V\);respectively. The simulation results in subthreshold regime of FinFET based two stage OTA has a gain of 57 dB with a phase margin of 69.81 degree, Common Mode Rejection Ratio (CMRR) of 61.55 dB and power consumption of 108 nW.

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Authors and Affiliations

  1. Sardar Patel Institute of Technology, Mumbai, India

    Reena Sonkusare & Surendra S. Rathod

  2. Indian Institute of Technology Bombay, Mumbai, India

    Prathamesh Milind Pilankar

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  1. Reena Sonkusare
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  2. Prathamesh Milind Pilankar
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  3. Surendra S. Rathod
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Correspondence to Reena Sonkusare.

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Sonkusare, R., Pilankar, P.M. & Rathod, S.S. Analysis of subthreshold SOI FinFET based two stage OTA for low power. Analog Integr Circ Sig Process 98, 277–289 (2019). https://doi.org/10.1007/s10470-018-1305-3

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