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Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

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Abstract

The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give the highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

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Acknowledgements

The authors thank to the department of Electronics and Communications Engineering, NIT Warangal for providing the TCAD Tools.

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Authors and Affiliations

  1. Department of Electronics & communication Engineering, National Institute of Technology Warangal, Warangal, Telangana, 506004, India

    V. Bharath Sreenivasulu & Vadthiya Narendar

Authors
  1. V. Bharath Sreenivasulu
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  2. Vadthiya Narendar
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Contributions

V. Bharath Sreenivasulu: Writing- Original draft preparation, Formal Analysis, Investigation, Simulation, Data Curation.

V. Narendar: Supervision, Resources.

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Correspondence to V. Bharath Sreenivasulu.

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Sreenivasulu, V.B., Narendar, V. Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching. Silicon 14, 10401–10411 (2022). https://doi.org/10.1007/s12633-022-01777-6

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