The Advanced Onboard Signal Processor (AOSP) Daniel J. Dechant OriginalPaper 01 October 1990 Pages: 69 - 78
The design of wave digital filters using fully pipelined bit-level systolic arrays Stuart LawsonSteve Summerfield OriginalPaper 01 September 1990 Pages: 51 - 64
Systolic square root covariance Kalman filtering F. M. F. GastonG. W. IrwinJ. G. McWhirter OriginalPaper 01 September 1990 Pages: 37 - 49
Systolic architectures for adaptive multichannel least squares lattice filters Paul S. Lewis OriginalPaper 01 September 1990 Pages: 29 - 36
A polyphase architecture for serial-input convolvers Luigi Dadda OriginalPaper 01 September 1990 Pages: 17 - 27
Configurable hardware: Two case studies of micro-grain computation Tom KeanJohn Gray OriginalPaper 01 September 1990 Pages: 9 - 16
Scalable VLSI implementations for neural networks D. van den BoutP. FranzonW. Liu OriginalPaper 01 April 1990 Pages: 367 - 385
A clock-free chip set for high-sampling rate adaptive filters Teresa H. -Y. MengRobert W. BrodersenDavid G. Messerschmitt OriginalPaper 01 April 1990 Pages: 345 - 365
Mapping dynamic programming onto a linear systolic array V. K. Prasanna KumarYu-Chen Tsai OriginalPaper 01 April 1990 Pages: 335 - 343
A case for digit serial VLSI signal processors Mary Jane IrwinRobert Michael Owens OriginalPaper 01 April 1990 Pages: 321 - 334
Systolic algorithms for some scheduling and graph problems Oscar H. IbarraTao JiangMichael A. Palis OriginalPaper 01 April 1990 Pages: 307 - 320
Efficient microcoded processor design for fixed rate DFT and FFT Francky CatthoorDirk LanneerHugo De Man OriginalPaper 01 April 1990 Pages: 287 - 306
Bidiagonalization and symmetric tridiagonalization by systolic arrays R. Schreiber OriginalPaper 01 April 1990 Pages: 279 - 285
An integrated automatic design system for complex DSP algorithms J. van MeerbergenJ. HuiskenH. De Man OriginalPaper 01 April 1990 Pages: 265 - 278
A VLSI structure forX(modm) operation Giuseppe AliaEnrico Martinelli OriginalPaper 01 April 1990 Pages: 257 - 264
A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem Fernando J. NúñezMateo Valero OriginalPaper 01 October 1989 Pages: 153 - 162
A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix Paul F. C. KrekelEd F. Deprettere OriginalPaper 01 October 1989 Pages: 143 - 152
Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms V. P. RoychowdhuryT. Kailath OriginalPaper 01 October 1989 Pages: 127 - 142
Scheduling a system of nonsingular affine recurrence equations onto a processor array Yoav YaacobyPeter R. Cappello OriginalPaper 01 October 1989 Pages: 115 - 125
The mapping of linear recurrence equations on regular arrays Patrice QuintonVincent van Dongen OriginalPaper 01 October 1989 Pages: 95 - 113
Parallel algorithms/architectures for neural networks J. N. HwangS. Y. Kung OriginalPaper 01 September 1989 Pages: 221 - 251
On the optimality of linear schedules Weijia ShangJose A. B. Fortes OriginalPaper 01 September 1989 Pages: 209 - 220
An efficient bit-level systolic cell design for finite ring digital signal processing applications G. A. JullienP. D. BirdW. C. Miller OriginalPaper 01 September 1989 Pages: 189 - 207
A novel fault tolerance technique for recursive least squares minimization Franklin T. LukEric K. TorngCynthia J. Anfinson OriginalPaper 01 September 1989 Pages: 181 - 188
Fast radix-2 division with quotient-digit prediction Miloš D. ErcegovacTomas Lang OriginalPaper 01 September 1989 Pages: 169 - 180
ASP modules: cost-effective building-blocks for real-time DSP systems R. M. Lea OriginalPaper 01 August 1989 Pages: 69 - 84
Cellular array processor CAP and applications Mitsuo IshiiHiroyuki SatoHiroaki Ishihata OriginalPaper 01 August 1989 Pages: 57 - 67
Parallel implementation of synthetic aperture radar algorithms K. Wojtek PrzytulaJ. Greg Nash OriginalPaper 01 August 1989 Pages: 45 - 56
A million transistor systolic array graphics engine Nader GharachorlooSatish GuptaChristos Zoulas OriginalPaper 01 August 1989 Pages: 35 - 43
Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP Takao NishitaniIchiro TamitaniKoichi Kikuchi OriginalPaper 01 August 1989 Pages: 25 - 34
Bit-Level systolic architectures for high performance IIR filtering S. C. KnowlesJ. G. McWhirterJ. V. McCanny OriginalPaper 01 August 1989 Pages: 9 - 24
