Abstract
Wave digital filters (WDF) based on analogue lattice and unit element cascade networks possess important properties that make them suitable for VLSI integration. These include low round-off noise even with short coefficient wordlength and a building block (two-port adaptor) with a very simple structure. Exploiting these properties leads to area efficient designs. Systolic architectures for these WDF networks give the additional advantage of very high sampling rates with potential application in sonar and video signal processing. The bit-level systolic array design of two WDFs is considered in detail, beginning at the filter specification and ending at the VLSI hardware architecture, with discussion of the expected values of the integrated circuit parameters.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
A. Fettweis, “Wave Digital Filters: Theory and Practice,”Proceedings of the IEEE, Vol. 74, pp. 270–327, 1986.
U. Kleine and T.G. Noll, “Wave Digital Filters Using Carry-Save Arithmetic,”ISCAS-88 Proceedings, Helsinki, pp. 1757–1762, 1988.
J. Pandel and U. Kleine, “Design of Bireciprocal Wave Digital Filters for High Sampling Rate Applications,”Frequenz, Vol. 40, pp. 300–308, 1986.
J.V. McCanny and J.G. McWhirter, “Implementation of Signal Processing Functions Using 1-Bit Systolic Arrays,”Electronics Letters, Vol. 18, pp. 241–243, 1982.
S.C. Knowles, R.F. Woods, J.G. McWhirter and J.V. McCanny, “A High Performance Systolic IIR Filter Architecture,”,IEE Colloquium Digest 1988/37-DSP for VLSI, pp. 2/1–2/4, 1988.
A.R. Mirzai and S.S. Lawson, “Bit-Level Systolic Adaptors for Wave Digital Filters,”ISCAS-86 Proceedings, San Jose, California, pp. 853–856, 1986.
S.S. Lawson and A.R. Mirzai, “Improved 2-Port Systolic Adaptor for Wave Digital Filters,”,IEE Proceedings, Part G, Vol. 136, pp. 121–125, (1989).
S.S. Lawson and S. Summerfield, “VLSI Implementation of Adaptors Using Systolic Arrays”,IEE Colloquium Digest 1988/37-DSP for VLSI, pp. 1/1–1/6, 1988.
A. Tomlinson and A.R. Mirzai, “Single-Chip 2-Port Adaptors for Wave Digital Filters,”Electronics Letters, Vol. 25, No. 23, pp. 1553–1555, 1989.
S. Summerfield and S.S. Lawson, “Application of Bit-Level Systolic Arrays to Pipelines Architectures for Wave Digital Filters,” inSystolic Array Processors, J. McCanny, et al., (Eds.), London: Prentice Hall, pp. 504–513, 1989.
S. Summerfield and S. S. Lawson, “VLSI Implementation of Wave Digital Filters Using Systolic Arrays,”ISCAS-90 Proceedings, New Orleans, 1990.
L. Gazsi, “Explicit Formulas for Lattice Wave Digital Filters,”IEEE Transactions on Circuits and Systems, Vol. CAS-32, pp. 68–88, 1985.
A. Mirzai and S.S. Lawson, “Finite Wordlength Design of Wave Digital Filters,”Electronics Letters, Vol. 22, pp. 851–853, 1986.
R. Levy, “Tables of Element Values for the Distributed Low-Pass Prototype Filter,”IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-13, pp. 514–536, 1965.
W. Wegener, “On the Design of Wave Digital Lattice Filters with Short Co-Efficient Wordlengths and Optimal Dynamic Range,”IEEE Transactions on Circuits and Systems, Vol. CAS-25, pp. 1091–1098, 1978.
J.S. Rajinder, R.F. Woods and J.V. McCanny, “High Performance Systolic Two-Port Adaptor for Wave Digital Filtering Application,”ICASSP-90 Proceedings, Albuquerque, New Mexico, 1990.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Lawson, S., Summerfield, S. The design of wave digital filters using fully pipelined bit-level systolic arrays. J VLSI Sign Process Syst Sign Image Video Technol 2, 51–64 (1990). https://doi.org/10.1007/BF00931036
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF00931036