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Efficient microcoded processor design for fixed rate DFT and FFT

  • Francky Catthoor
  • Dirk Lanneer
  • Hugo De Man
Article

Abstract

Many Fourier transform applications have to operate at fixed sample rates in the low to medium range, especially in signal processing systems. Hence, in order to arrive at efficient implementations, hardware-sharing is required as in microcoded architectures. In this paper, very efficient application-specific realizations spanning a wide throughput range are proposed for both DFT and FFT algorithms. Novel single-cycle address computations are presented for the FFT to obtain these results. Trade-offs between the architectural alternatives are provided too. These designs have been used as test-vehicles for the architectural strategy in an automated synthesis tool-box tuned towards signal processing applications.

Keywords

Idle Cycle Pitch Extraction IEEE Custom Integrate Circuit Background Memory Butterfly Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    J. Allen, “Computer architecture for digital signal processing,”Proc. IEEE, vol. 73, no. 5, May 1985, pp 854–873.CrossRefGoogle Scholar
  2. 2.
    F. Catthoor,Architectural design strategies for complex DSP-systems in an automated synthesis environment, Doctoral dissertation, ESAT, K.U. Leuven, Belgium, May 1987.Google Scholar
  3. 3.
    F. Catthoor, J. Rabaey, G. Goossens, J. Van Meerbergen, R. Jain, H. De Man, and J. Vandewalle, “Architectural Strategies for an Application-Specific Synchronous Multi-Processor Environment,”IEEE Trans., Acoustics, Speech and Signal Processing, vol. 36, 1988, pp. 265–284.CrossRefGoogle Scholar
  4. 4.
    H. De Man, J. Rabaey, and P. Six, “CATHEDRAL-II: a synthesis and module generation system for multiprocessor systems on a chip,”Workshop of the NATO Advanced Study Institute on “Logic Synthesis and Silicon Compilation for VLSI,” L'Aquila, Italy, July 1986.Google Scholar
  5. 5.
    H. De Man, J. Rabaey, J. Huisken, and J. Van Meerbergen, “Silicon compilation of DSP systems with CATHEDRAL-II,”ESPRIT technical week, Brussels, Belgium, Sept. 1987.Google Scholar
  6. 6.
    J. Rabaey, H. De Man, J. Vanhoof, G. Goossens, and F. Catthoor, “CATHEDRAL-II: A synthesis system for multi-processor DSP systems,” InSilicon Compilation. Edited by D. Gajski, Reading, MA: Addison-Wesley, 1988, pp. 311–360.Google Scholar
  7. 7.
    P.B. Denyer and D. Renshaw,VLSI Signal Processing: A Bit-Serial Approach, Reading, MA: Addison-Wesley, 1985.Google Scholar
  8. 8.
    J. Van Ginderdeuren, H. De Man, F. Catthoor, and S. Beckers, “A design methodology for compact integration of wave digital filters,”Digest Europ. Conf. on Solid-State Circuits, ESSCIRC, Edinburgh, U.K., Sept. 1984, pp. 210–213.Google Scholar
  9. 9.
    F. Catthoor, D. De Man, and J. Vandewalle, “Bit-serial VLSI implementation for an optimized transmultiplexer design,”Int. Journal of Circuit Theory and Appl., vol. 15, 1987, pp. 281–303.CrossRefGoogle Scholar
  10. 10.
    F. Catthoor, and H. De Man, “Application-specific architectural methodologies for high-throughput digital signal and image processing,”IEEE Trans. on Acoustics, Speech and Signal Processing, (in press).Google Scholar
  11. 11.
    H. De Man, “Evolution of CAD-tools towards third generation custom VLSI-design,”Design Europ. Conf. on Solid-State Circuits, ESSCIRC, Toulouse, France, Sept. 1985, pp. 256–256c.Google Scholar
  12. 12.
    W.A. Perera and P. Rayner, “Optimal design of multiplierless DFTs and FFTs,”Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Tokyo, Japan, April 1986, pp. 6.9.1–4.Google Scholar
  13. 13.
    L. Rabiner and B. Gold,Theory and Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice Hall, 1975.Google Scholar
  14. 14.
    R. Holm and R. Jones, “Use discrete Fourier transforms to simplify signal processing,”EDN Journal, April 1983, pp. 203–216.Google Scholar
  15. 15.
    R.J. Sluyter, H.J. Kotmans, and A. Van Leeuwaarden, “A novel method for pitch extraction from speech and a hardware model applicable to vocoder systems,”Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Denver, CO, April 1980, pp. 45–48.Google Scholar
  16. 16.
    R.J. Slyyter, H.J. Kotmans, and A. Van Leeuwaarden, “Advanced chips usher in a new era for digital signal processing,”Electronic Design, Feb. 1986, pp. 129–174.Google Scholar
  17. 17.
    S.S. Magar, “Architecture and applications of a programmable monolithic digital signal processor—a tutorial overview,”Proc. IEEE Int. Symp. on Circuits and Systems, Montreal, Canada, May 1984, pp. 944–950.Google Scholar
  18. 18.
    P.E. Papamichalis, “FFT implementation on the TMS320C30,”Proc. Int. Conf. on Acoustics, Speech and Signal Processing, New York, April 1988, pp. 1399–1402.Google Scholar
  19. 19.
    K. Yamashita, A. Kanasugi, S. Hijiya, G. Goto, N. Matsumura, and T. Shirato, “A wafer-scale 170.000 gate FFT processor with built-in test circuits,”Proc. IEEE Custom Integrated Circuits Conf., Portland, OR, May 1987, pp. 207–210.Google Scholar
  20. 20.
    R.W. Linderman, C.G. Shepard, K. Taylor, P.W. Coutee, P.C. Rossbach, and J.M. Collins, “A 70 MHz 1.2 micron CMOS 16-point DFT processor,”Proc. IEEE Custom Integrated Circuits Conf., Portland, OR, May 1987, pp. 219–222.Google Scholar
  21. 21.
    J. Van Meerbergen, F. Welten, F. Van Wijk, J. Stoter, J. Huisken, A. Delaruelle, and K. Van Eerdewijk, “An 8 MIPS CMOS digital signal processor,”Proc. IEEE Int. Solid-State Circ. Conf., Anaheim, CA, Feb. 1986, pp. 84–85.Google Scholar
  22. 22.
    P. Kabal and P. Sayar, “Performance of fixed-point FFTs: rounding and scaling considerations,”Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Tokyo, Japan, April 1986, pp. 6.3.1–4.Google Scholar
  23. 23.
    G. Goossens, J. Vandewalle, and H. De Man, “Loop optimization in register-transfer scheduling for DSP systems,”Proc. 26th ACM/IEEE Design Automation Conf., Las Vegas, Texas, June 1989. pp. 826–831.Google Scholar
  24. 24.
    J. Van Meerbergen, “Some comments on the Comparison DFT-FFT,” ESPRIT97 internal report, Philips NATLAB, Eindhoven, June 1986.Google Scholar
  25. 25.
    N.A. Ramakrishna and M.A. Bayoumi, “A testable CMOS signal processor for Fast Fourier Transforms,”Proc. IEEE Int. Symp. on Circuits and Systems, Helsinki, Finland, June 1988, pp. 73–76.Google Scholar
  26. 26.
    W.T. Krakow, W.E. Batchelor, W. Liu, T. Hildebrandt, T. Hughes, T. Yeh, R. Salama, and G. Mei, “Design and implementation of a two-dimensional Fast Fourier Transform chip,”Proc. IEEE Custom Integrated Circuits Conf., Rochester, NY, May 1988, pp. 8.4.1–4.Google Scholar
  27. 27.
    J.T. Rayfield and H.F. Silverman, “Implementation of a 2-D DFT algorithm on a loosely-coupled parallel system,”Proc. Int. Conf. on Acoustics, Speech and Signal Processing, New York, April 1988, pp. 1997–2001.Google Scholar
  28. 28.
    S.S. Magar, S. Shen, G. Luikuo, M. Fleming, and R. Aguilar, “An application specific DSP chip set for 100 MHz data rates,”Proc. Int. Conf. on Acoustics, Speech and Signal Processing, New York, April 1988, pp. 1989–1993.Google Scholar
  29. 29.
    W. Kellerman, “Analysis and design of multirate systems for cancellation of acoustic echos,”Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, New York, April 1988, pp. 2570–2573.Google Scholar
  30. 30.
    Jiande Chen, Hugo Bes, Joos Vandewalle, and Paul Janssens, “A new structure for sub-band acoustic echo canceller,”Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, New York, April 1988, pp. 2574–2577.Google Scholar
  31. 31.
    J. Vanhoof, J. Rabaey, and H. De Man, “A knowledge based CAD system for synthesis of multi-processor digital signal processing chips,”Proc. VLSI '87, Int. Conf. on VLSI, Vancouver, Canada, Aug. 1987.Google Scholar
  32. 32.
    D. Lanneer, F. Catthoor, G. Goossens, M. Pauwels, J. Van Meerbergen, H. De Man, “Open ended system for high-level synthesis of flexible signal processors,”Proc. Europ. Design Autom. Conf., Paris, France, April 1990.Google Scholar

Copyright information

© Kluwer Academic Publishers 1990

Authors and Affiliations

  • Francky Catthoor
    • 1
  • Dirk Lanneer
    • 1
  • Hugo De Man
    • 1
  1. 1.Inter-University Micro-Electronic CenterHeverleeBelgium

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