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Abstract

An integrated design environment for the automated design of DSP systems is described. The overall design time of complex DSP systems on silicon can be reduced drastically by offering the designer a complete silicon compilation environment, integrating architectural level synthesis tools, a module generator and a floorplanner. The system is supported by a flexible and powerful library. A true exploration of the design space in an interactive way is possible. Examples of the first complex chips that have been designed with this system are discussed.

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References

  1. D. Gajski,Silicon Compilation, Reading, MA: Addison-Wesley, 1988.

    Google Scholar 

  2. M. McFarland, A. Parker, and P. Camposano, “Tutorial on high-level synthesis,”Proceedings of the 25th IEEE/ACM Design Automation Conference, June 1988, pp. 330–336.

  3. D.E. Thomas, E.M. Dirkes, R.A. Walker, J.V. Rajan, J.A. Nestor, and R.L. Blackburn, “The system architect's workbench,”Proceedings of the 25th IEEE/ACM Design Automation Conference, June 1988, pp. 337–343.

  4. C.J. Tseng and D.P. Siewiorek, “Facet: A procedure for the automated synthesis of digital systems,”Proceedings of the 20th IEEE/ACM Design Automation Conference, 1983, pp. 490–496.

  5. H. Trickey, “FLAMEL: A high-level hardware compiler,”IEEE Transactions on CAD, vol. CAD-6, 1987, pp. 259–269.

    Article  Google Scholar 

  6. P. Marwedel, “A new synthesis algorithm for the mimola software system,”Proceedings of the 23rd IEEE/ACM Design Automation Conference, 1986, pp. 271–277.

  7. A.C. Parker, G.T. Pizarro, and M. Mlinar, “MAHA: A program for datapath synthesis,”Proceedings of the 23rd Design Automation Conference, July 1986, pp. 461–466.

  8. P.G. Paulin and J.P. Knight, “Force-directed scheduling in automatic data path synthesis,”Proceedings of the 24th IEEE/ACM Design Automation Conference, Miami, July 1987, pp. 195–202.

  9. M. McFarland, “Reevaluating the design space for registertransfer synthesis,”Proc. IEEE Int. Conf. on Computer-Aided Design, Santa Clara, November 1987, pp. 262–265.

  10. P. Denyer and D. Renshaw,VLSI Signal Processing: A Bit Serial Approach, Reading, MA: Addison-Wesley, 1985.

    Google Scholar 

  11. J. Van Ginderdeuren, H. De Man, B. De Loore, H. Vanden Wijngaert, A. Delaruelle, and G. Van den Audenaerde, “A high-quality digital audio filter set designed by silicon compiler CATHEDRAL I,”IEEE Journal of Solid State Circuits, vol. SC-21, 1986, pp. 1067–1075.

    Article  Google Scholar 

  12. J. Jessica and D. Hartley, “Behavioral to structural translation in a bit serial silicon compiler,”IEEE Transactions on Computer-Aided Design, vol. 7, 1988, pp. 229–239.

    Google Scholar 

  13. J. Rabaey, S. Pope, and R. Broderson, “An integrated automatic layout generation system for DSP circuits,”IEEE Transactions on Computer Aided Design, vol. CAD-4, 1985, pp. 285–296.

    Article  Google Scholar 

  14. J. Schuck, M. Glesner, and M. Lacken, “First results and design experience with silicon Compiler ALGIC,” InVLSI Signal Processing II, New York: IEEE Press, 1986.

    Google Scholar 

  15. A.E. Casavant, M.A. D'Abreu, M. Dragomirecky, D.A. Duff, J.R. Jasica, M.J. Hartman, K.S. Hwang, and W.D. Smith, “A synthesis environment for designing DSP systems,”IEEE Design and Test of Computers, April 1989, pp. 35–44.

  16. B. Haroun and M. Elmasry, “SPAID: An archietectural synthesis tool for DSP custom applications,”IEEE Journal of Solid State Circuits, vol. 24, 1989, pp. 426–435.

    Article  Google Scholar 

  17. J. Huisken, H. Janssen, P. Lippens, O. McArdle, R. Segers, P. Zegers, A. Delaruelle, and J. Van Meerbergen, “Efficient design of systems on silicon with PIRAMID,” InLogic and Architecture Synthesis for Silicon Compilers, Amsterdam: North-Holland, 1989, pp. 299–311.

    Google Scholar 

  18. F. Catthoor, J. Rabaey, G. Goossens, J. Van Meerbergen, R. Jain, H. De Man, and J. Vandewalle, “Architectural strategies for an application-specific synchronous multi-processor environment,”IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 36, 1988, pp. 265–284.

    Article  Google Scholar 

  19. H. De Man, J. Rabaey, J. Huisken, and J. Van Meerbergen, “Silicon compilation of DSP systems with CATHEDRAL II,” InEsprit '87 Achievements and Impact, Amsterdam: North-Holland, September 1987, pp. 207–217.

    Google Scholar 

  20. H. De Man, J. Rabaey, P. Six, and L. Claesen, “CATHEDRAL II. A silicon compiler for digital signal processing,”IEEE Design and Test, Dec. 1986, pp. 13–25.

  21. P. Hilfinger, “A high-level language and silicon compiler for digital signal processing,”Proc. IEEE Custom Integrated Circuits Conference, Portland, May 1985, pp. 213–216.

  22. J. Decaluwe, J. Rabaey, J. Van Meerbergen, and H. De Man, “Interprocessor communication in synchronous multiprocessor digital signal processing chips,”IEEE Transactions on Acoustics, Speech and Signal Processing, (in press).

  23. J. Vanhoof, J. Rabaey, and H. De Man, “A knowledge based CAD system for synthesis of multiprocessor digital signal processing chips,”Int. Conf. on Very Large Scale Integration, Vancouver, Aug. 1987, pp. 73–88.

  24. G. Goossens, D. Lanneer, J. Vanhoof, J. Rabaey, J. Van Meerbergen, and H. De Man, “Optimization based synthesis of multiprocessor chips for digital signal processing with CATHEDRAL II,” InLogic and Architecture Synthesis for Silicon Compilers, Amsterdam: North-Holland, 1989.

    Google Scholar 

  25. K. Croes, H. De Man, and P. Six, “Cameleon, a process tolerant symbolic layout system,”IEEE Journal of Solid State Circuits, vol. 23, 1988, pp. 705–713.

    Article  Google Scholar 

  26. L. Matterne, J. Van Meerbergen, F. Beenker, V. Mehra, J. Theunissen, and R. Segers, “A C-testable Booth multiplier designed for a silicon compilation environment,”Proc. International Conference on Computer Design, New York, 1987, pp. 354–357.

  27. F. Beenker, K. van Eerdewijk, R. Gerritsen, F. Peacock, and M. van der Star, “Macro testing: unifying IC and board test,”IEEE Design and Test, Dec. 1986, pp. 26–32.

  28. G.J. Bosscha and R.J. Sluyter, “A DFT vocoder using harmonic sieve pitch extraction,”Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, Paris, April 1980, pp. 1952–1955.

  29. R.J. Sluyter, H.J. Kotmans, and A. van Leeuwarden, “A novel method for pitch extraction from speech and a hardware model applicable to vocoder systems,”Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, Paris, April 1980, pp. 45–48.

  30. A.E. Filip, “Linear approximations to\(\sqrt {x^2 + y^2 } \) having equiripple error characteristics,”IEEE Transactions on Audio and Electroacoustics, vol. AU-21, 1973, pp. 554–556.

    Article  Google Scholar 

  31. J. Van Meerbergen, “Efficient controller architectures for DSP compilers,”Proceedings of the IEEE Custom Integrated Circuits Conference, Rochester, May 1988, pp. 14.5.1–14.5.4.

  32. A. Delaruelle, “Design of a syndrome generator chip using the PIRAMID design system,”Digest of the 14th European Solid-State Circuit Conference, Manchester, 1988, pp. 256–259.

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van Meerbergen, J., Huisken, J., Lippens, P. et al. An integrated automatic design system for complex DSP algorithms. J VLSI Sign Process Syst Sign Image Video Technol 1, 265–278 (1990). https://doi.org/10.1007/BF00929921

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