Journal of VLSI Signal Processing

, Volume 2, Issue 2, pp 79–87 | Cite as

The 3-D Computer

  • M. J. Little
  • R. D. Etchells
  • J. Grinberg
  • S. P. Laub
  • J. G. Nash
  • M. W. Yung
Article

Abstract

The 3-D Computer [1]–[4] is a unique implementation of a cellular array processor. We have developed two radically new technologies which enable massive numbers of communication channels both between silicon wafers and through them. A parallel processor (single instruction-multiple data stream cellular array processor) has been designed and built to demonstrate the potential of this technological approach. While the 3-D Computer which has been built and operated in a small scale implementation relative to the long-term aims of this technology, it is nevertheless an extremely powerful computer. The current feasibility demonstration 3-D Computer is a 32×32 array of processors partitioned over five wafers stacked one on top of another. The throughput of this current machine is >600 million operations per second (MOPS) with a 10 MHz clock, while the projected throughput of a full scale machine is >100 billion operations per second (BOPS), again with a 10 MHz clock. The extension of the level of circuit integration beyond that of VLSI and WSI, which is made possible by the 3-D technologies of wafer feedthroughs and microbridges, enable us to achieve these enormous throughputs in a very compact form and at very low power. The small size and low power attributes of the 3-D Computer result from the elimination of the chip level and board level packaging and the intraboard wiring required by conventional levels of circuit integration.

Keywords

NASH Silicon Wafer Circuit Integration Cellular Array Wafer Scale Integration 

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References

  1. 1.
    M.J. Little, R.D. Etchells, J. Grinberg, S.P. Laub, J.G. Nash, and M.W. Yung, “The 3-D Computer,”Proc. IEEE Int. Conf. on Wafer Scale Integration, San Francisco, 1989.Google Scholar
  2. 2.
    J.M. Kallis, L.B. Duncan, S.P. Laub, M.J. Little, L.M. Miani, and D.C. Sandkulla, “Reliability of the 3-D Computer under Stress of Mechanical Vibration and Thermal Cycling,”Proc. IEEE Int. Conf. on Wafer Scale Integration, San Francisco, 1989.Google Scholar
  3. 3.
    M.W. Yung, M.J. Little, R.D. Etchells, J.G. Nash, “Redundancy for Yield Enhancement in the 3-D Computer,”Proc. IEEE Int. Conf. on Wafer Scale Integration, San Francisco, 1989.Google Scholar
  4. 4.
    M.L. Campbell, M.J. Little, M.W. Yung, “Hierarchical Fault Tolerance for 3-D Microelectronics”Proc. IEEE Int. Conf. on Wafer Scale Integration, San Francisco, California, 1990.Google Scholar

Copyright information

© Kluwer Academic Publishers 1990

Authors and Affiliations

  • M. J. Little
    • 1
  • R. D. Etchells
    • 1
  • J. Grinberg
    • 1
  • S. P. Laub
    • 1
  • J. G. Nash
    • 1
  • M. W. Yung
    • 1
  1. 1.Hughes Research LaboratoriesMalibu

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