1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes 01 March 2008 Pages: 1 - 1

2. New Editors

   Acknowledgments 01 March 2008 Pages: 3 - 4

3. Test Technology Newsletter February 2008

   News 04 March 2008 Pages: 5 - 6

4. List of 2007 Reviewers

   Acknowledgments 01 March 2008 Pages: 7 - 8

5. Guest Editorial

   • Nur Touba
   • Adelio Salsano
   • Minsu Choi

   EditorialNotes 01 March 2008 Pages: 9 - 10

6. Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger

   • Yoichi Sasaki
   • Kazuteru Namba
   • Hideo Ito

   OriginalPaper 04 January 2008 Pages: 11 - 19

   

7. Error Detection Enhancement in PowerPC Architecture-based Embedded Processors

   • Mahdi Fazeli
   • Reza Farivar
   • Seyed Ghassem Miremadi

   OriginalPaper 19 February 2008 Pages: 21 - 33

   

8. Software and Hardware Techniques for SEU Detection in IP Processors

   • C. Bolchini
   • A. Miele
   • M. Violante

   OriginalPaper 29 January 2008 Pages: 35 - 44

   

9. Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs

   • Eduardo Luis Rhod
   • Carlos Arthur Lang Lisbôa
   • Massimo Violante

   OriginalPaper 05 January 2008 Pages: 45 - 56

   

10. A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

    • Rui Gong
    • Wei Chen
    • Zhiying Wang

    OriginalPaper 05 January 2008 Pages: 57 - 65

    

11. Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding

    • Amlan Ganguly
    • Partha Pratim Pande
    • Cristian Grecu

    OriginalPaper 05 January 2008 Pages: 67 - 81

    

12. Majority Logic Mapping for Soft Error Dependability

    • Lorenzo Petroli
    • Carlos Arthur Lang Lisboa
    • Luigi Carro

    OriginalPaper 05 January 2008 Pages: 83 - 92

    

13. Checkers’ No-Harm Alarms and Design Approaches to Tolerate Them

    • Daniele Rossi
    • Martin Omaña
    • Cecilia Metra

    OriginalPaper 26 January 2008 Pages: 93 - 103

    

14. Analysis and Evaluations of Reliability of Reconfigurable FPGAs

    • Salvatore Pontarelli
    • Marco Ottavi
    • Adelio Salsano

    OriginalPaper 17 January 2008 Pages: 105 - 116

    

15. Hierarchical Verification for Increasing Performance in Reliable Processors

    • Joonhyuk Yoo
    • Manoj Franklin

    OriginalPaper 16 January 2008 Pages: 117 - 128

    

16. Performance-Optimized Design for Parametric Reliability

    • Ramyanshu Datta
    • Jacob A. Abraham
    • Kevin J. Nowka

    OriginalPaper 04 January 2008 Pages: 129 - 141

    

17. Design Considerations for High Performance RF Cores Based on Process Variation Study

    • Shambhu Upadhyaya
    • Nandakumar P. Venugopal
    • Prerna Mayor

    OriginalPaper 30 January 2008 Pages: 143 - 155

    

18. Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy

    • Kristian Granhaug
    • Snorre Aunet

    OriginalPaper 10 January 2008 Pages: 157 - 163

    

19. Defect Analysis and Defect Tolerant Design of Multi-port SRAMs

    • Lushan Liu
    • Pradeep Nagaraj
    • Ramalingam Sridhar

    OriginalPaper 17 January 2008 Pages: 165 - 179

    

20. A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy

    • Da-Ming Chang
    • Jin-Fu Li
    • Yu-Jen Huang

    OriginalPaper 04 January 2008 Pages: 181 - 192

    

21. Substrate Testing on a Multi-Site/Multi-Probe ATE

    • Xiaojun Ma
    • Fabrizio Lombardi

    OriginalPaper 08 January 2008 Pages: 193 - 201

    

22. On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

    • Kyriakos Christou
    • Maria K. Michael
    • Spyros Tragoudas

    OriginalPaper 08 January 2008 Pages: 203 - 222

    

23. Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X–Y Zoning Method

    • Yukiya Miura
    • Jiro Kato

    OriginalPaper 05 January 2008 Pages: 223 - 233

    

24. Scan Test Response Compaction Combined with Diagnosis Capabilities

    • Sverre Wichlund
    • Frank Berntsen
    • Einar Johan Aas

    OriginalPaper 15 January 2008 Pages: 235 - 246

    

25. Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

    • Zhiyuan He
    • Zebo Peng
    • Bashir M. Al-Hashimi

    OriginalPaper 30 January 2008 Pages: 247 - 257

    

26. A Methodology for Handling Complex Functional Constraints for Large Industrial Designs

    • Abhijit Jas
    • Yi-Shing Chang
    • Sreejit Chakravarty

    OriginalPaper 06 February 2008 Pages: 259 - 269

    

27. Monomer Control for Error Tolerance in DNA Self-Assembly

    • Byunghyun Jang
    • Yong-Bin Kim
    • Fabrizio Lombardi

    OriginalPaper 04 January 2008 Pages: 271 - 284

    

28. Bilateral Testing of Nano-scale Fault-Tolerant Circuits

    • Lei Fang
    • Michael S. Hsiao

    OriginalPaper 08 January 2008 Pages: 285 - 296

    

29. Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA

    • X. Ma
    • J. Huang
    • F. Lombardi

    OriginalPaper 08 January 2008 Pages: 297 - 311

    

30. Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design

    • Myungsu Choi
    • Minsu Choi

    OriginalPaper 04 January 2008 Pages: 313 - 320