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Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

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Abstract

High temperature has become a major problem for system-on-chip testing. In order to reduce the test application time while keeping the temperatures of the cores under test within safe ranges, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test application time and, at the same time, prevent the temperatures of cores under test going beyond given limits. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling periods between test sequences so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, such that the cooling periods and the bandwidth of the test bus can be utilized for test data transportation, and hence the test application time can be reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use the constraint logic programming (CLP) to build the optimization model and find the optimal solution. As the optimization time of the CLP-based approach increases exponentially with the problem size, we also propose a heuristic which generates longer test schedules but requires substantially shorter optimization time. Experimental results have shown the efficiency of the proposed approach.

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Notes

  1. We assume that the CUT is at the ambient temperature when the first test sequence starts. We also assume that the first test sequence is partitioned such that it can be continuously applied until the core temperature reaches the temperature limit.

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Acknowledgment

This work is partially supported by the Swedish Foundation for Strategic Research (SSF) under the Strategic Integrated Electronic Systems Research (STRINGENT) program through grants to Zhiyuan He, Zebo Peng, and Petru Eles. Funded in part by the EPSRC (UK) grants GR/S05557 and GR/S95770 to Paul Rosinger and Bashir M. Al-Hashimi.

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Authors and Affiliations

  1. Embedded Systems Laboratory, Department of Computer and Information Science, Linköping University, 581 83, Linköping, Sweden

    Zhiyuan He, Zebo Peng & Petru Eles

  2. School of Electronics and Computer Science, University of Southampton, SO17 1BJ, Southampton, UK

    Paul Rosinger & Bashir M. Al-Hashimi

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  1. Zhiyuan He
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  2. Zebo Peng
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  3. Petru Eles
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  4. Paul Rosinger
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  5. Bashir M. Al-Hashimi
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Correspondence to Zhiyuan He.

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Responsible Editor: N. A. Touba

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He, Z., Peng, Z., Eles, P. et al. Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. J Electron Test 24, 247–257 (2008). https://doi.org/10.1007/s10836-007-5030-6

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