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A Methodology for Handling Complex Functional Constraints for Large Industrial Designs

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Abstract

Functional constraints capture Boolean relationships among signal nets by analyzing the functionality of a circuit. Such constraints find widespread application in VLSI design methodology and can be derived using various techniques. The size and complexity of these constraints becomes a limiting factor in their successful usage for large designs. This paper describes CONAN (Constraint Analyzer), a powerful framework to analyze and simplify such constraints. CONAN is built on the solution to a novel minimization problem. The feasibility and effectiveness of CONAN is demonstrated by using it for functional untestability analysis of large industrial benchmarks. Run-times were reduced from over a week to less than 30 minutes. Additionally, unique functionally untestable faults were derived using this approach when compared with constraints provided by designers.

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Authors and Affiliations

  1. Design Technology and Solutions, Intel Corporation, Folsom, CA, 95630, USA

    Yi-Shing Chang

  2. Design Technology and Solutions, Intel Corporation, Austin, TX, 78746, USA

    Abhijit Jas

  3. Network Storage Product Group, LSI Corporation, Milpitas, CA, 95035, USA

    Sreejit Chakravarty

Authors
  1. Abhijit Jas
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  2. Yi-Shing Chang
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  3. Sreejit Chakravarty
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Correspondence to Yi-Shing Chang.

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Responsible Editor: N. A. Touba

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Jas, A., Chang, YS. & Chakravarty, S. A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J Electron Test 24, 259–269 (2008). https://doi.org/10.1007/s10836-007-5024-4

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  • DOI: https://doi.org/10.1007/s10836-007-5024-4

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