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Substrate Testing on a Multi-Site/Multi-Probe ATE

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Abstract

This paper presents a novel method that utilizes multi-site and multi-probe capabilities of an ATE for testing of pre-assembly MCM substrates. Testing multiple SUTs (substrates under test) simultaneously can improve the efficiency of the probes in an ATE and considerably reduce the total test time. An analytical model that predicts very accurately the testing time of a SUT batch is proposed. Based on this model, the optimal multi-site testing configuration as corresponding to the batch size can be established. Simulation results for an ATE with 12 flying-probes as an example of a commercially available tester are provided; for this ATE the proposed method achieves a reduction of 54.66% in test time over a single-site method (both at complete coverage of the modeled faults).

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Notes

  1. The next section will show the reasons behind the need for three tests.

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Authors and Affiliations

  1. ECE Department, Northeastern University, Boston, MA, 02115, USA

    Xiaojun Ma & Fabrizio Lombardi

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  1. Xiaojun Ma
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  2. Fabrizio Lombardi
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Correspondence to Xiaojun Ma.

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Responsible Editor: N. A. Touba

This manuscript is an extended version of a paper presented at the 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct 2006.

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Ma, X., Lombardi, F. Substrate Testing on a Multi-Site/Multi-Probe ATE. J Electron Test 24, 193–201 (2008). https://doi.org/10.1007/s10836-007-5038-y

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  • DOI: https://doi.org/10.1007/s10836-007-5038-y

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