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Error Detection Enhancement in PowerPC Architecture-based Embedded Processors

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Abstract

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer are combined with the Branch Trace Exception mechanism. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI) and Power Supply Disturbances fault injection (PSD). A total of 6,000 faults were injected in microcontroller to measure the error detection coverage of the proposed control flow checking technique. The experimental results show that this technique detects about 95.2% of transient errors in software implemented fault injection method and 96.4% of transient errors in power supply disturbances fault injection method.

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References

  1. Alkhalifa Z, Nair VSS, Krishnamurthy N, Abraham JA (1999) Design and evaluation of system-level checks for on-line control flow error detection. IEEE Trans Parallel Distrib Syst 10(6):627–641, June

    Article  Google Scholar 

  2. Arlat J, Crouzet Y, Carlson J, Folkeson P, Futchs E, Lenbers H (2003) Comparison of physical and software-implemented fault injection techniques. IEEE Trans Comput 52(9):1115–1133 (Sept)

    Article  Google Scholar 

  3. Avizienis A (2004) A fault tolerance infrastructure for high-performance COTS-based computing in dependable space systems. Proc. of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC’04), pp 336, March

  4. Bakhoda A, Miremadi SG, Zarandi H (2005) Experimental evaluation of transient effects on SRAM-based FPGA chips. In the Proceeding of 17th IEEE International Conference on Microelectronics (ICM’05), Islamabad, Pakistan, pp 251–255, Dec 13–15

  5. Barbosa R, Vinter J, Folkesson P, Karlsson J Assembly-level pre-injection analysis for improving fault injection efficiency

  6. Chevochot P, Puaut I (2001) Experimental evaluation of the fail-silent behavior of a distributed teal-time run-time support built from COTS components. Proc. of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’01), pp 304–313, July

  7. Croll P, Nixon P (1991) Developing safety-critical software within a CASE environment. IEE Colloquium on Computer Aided Software Engineering Tools for Real-Time Control, pp 8, Apr

  8. Freescale Semiconductor Company, PowerPC processors, http://www.freescale.com

  9. Gill CD, Cytron RK, Schmidt DC (2003) Multiparadigm scheduling for distributed real-time embedded computing. Proc IEEE 91(1):183–197, Jan

    Article  Google Scholar 

  10. Goloubeva O, Rebaudengo M, Sonza MR, Violante M (2003) Soft-error detection using control flow assertions. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’03), Boston, Massachusetts, pp 57–62, Nov

  11. Kanawati GA, Nair VSS, Krishnamurthy N, Abraham JA (1996) Evaluation of integrated system-level checks for on-line error detection. Proc. of lEEE Intemational Computer Performance and Dependability Symposium, pp 292–301

  12. Kontron Embedded Computers AG, ETX-P3M User’s Guide, 2003, URL: http://www.kontron.com

  13. Madeira H, Rela M, Furtado P, Silva JG (1992) Time behaviour monitoring as an error detection mechanism. 3rd IFIP Working Conference on Dependable Computing for Critical Applications (DCCA-3), pp 121–132, Sept

  14. Madeira H, Some RR, Moreira F, Costa D, Rennels D (2002) Experimental evaluation of a COTS system for space applications. Proc. of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’02), pp 325–330, June

  15. Mahmood A, McCluskey EJ (1988) Concurrent error detection using watchdog processors— a survey. IEEE Trans Comput 160–174, Feb

  16. McFearin L, Nair VSS (1995) Control-flow checking using assertions. Proc. of the IFIP Int’l Working Conf. Dependable Computing for Critical Applications (DCCA-5), Urbana-Champaign, IL, USA, 1995, pp 103–112, Sept

  17. Michel T, Leveugle R, Saucier G (1991) A new approach to control flow checking without program modification. 21st Int. Symposium on Fault-Tolerant Computing, pp 334–341

  18. Miremadi G, Karlsson J, Gunneflo U, Torin J (1992) Two software techniques for on-line error detection. Proc. FTCS-22, pp 328–335

  19. Miremadi G, Ohlsson J, Rimen M, Karlsson J (1998) Use of time, location and instruction signatures for control flow checking. Proc. of the DCCA-6 International Conference, IEEE Computer Society Press

  20. Miremadi G, Torin J (1995) Evaluation processor-behavior three error-detection mechanisms using physical fault-injection. IEEE Trans Reliab 44(3):441–453, Sept

    Article  Google Scholar 

  21. NASA office of logic design, “a scientific study of the problems of digital engineering for space flight systems”, http://klabs.org/DEI/Processor/PowerPC

  22. Nicolescu B, Velazco1 R, Sonza-Reorda M 2, Rebaudengo2 M, Violante M (2002) A software fault tolerance method for safety-critical systems: effectiveness and drawbacks. Proceedings of the 15th Symposium on Integrated Circuits and Systems Design (SBCCI’02), pp 101–106

  23. Oh N, Shirvani PP, McCluskey EJ (2002) Control-flow checking by software signatures. IEEE Trans Reliab 51(2):111–122, March

    Article  Google Scholar 

  24. Oh N, Shirvani PP, McCluskey EJ (2002) Error detection by duplicated instructions in super-scalar processors. IEEE Trans Reliab 51(1):63–75, Mar

    Article  Google Scholar 

  25. Pataricza A, Majzik I, Hohl W, Hoenig J (1993) Watchdog processors in parallel systems. Proc. of 19th Symposium on Microprocessing and Microprogramming (EUROMICRO’93), Barcelona, Spain, pp 69–74

  26. PCI Industrial Computer Manufactures Group, CompactPCI Industrial Boards, http://www.picmg.org

  27. Rajabzadeh A (2005) Error detection capability enhancement in COTS processor-based systems. Phd thesis, Sharif University of technology, Feb

  28. Rajabzadeh A, Miremadi G (2004) Transient detection in COTS processors using software approach. Elsevier Journal of Microelectronics Reliability

  29. Rajabzadeh A, Miremadi SG, Mohandespour M (2004) Experimental evaluation of master/checker architecture using power supply- and software-based fault injection. Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), Madeira Island, Portugal, pp 239–244, July

  30. Rajabzadeh A, Mohandespour M, Miremadi G (2004) Evaluation of a dependable architecture, vol 2. Proceedings of 9th CSI Computer Conference (CSICC 2004), Tehran, Iran, February, pp 249–254

  31. Rimen M (1995) Fault injection for studying error behavior and validation of error detection mechanisms. Ph.D. Thesis, Department of Computer Engineering, Chalmers University of Technology, Sweden

  32. Rimén M, Ohlsson J, Karlsson J (1995) Experimental evaluation of control flow errors. Proc. 1995 Pacific Rim International Symposium on Fault Tolerant Systems (PRFTS). IEEE Computer Society Press, Newport Beach, CA, USA, pp 238–243, December

    Google Scholar 

  33. Schuette MA, Shen JP (1987) Processor control flow monitoring using signatured instruction streams. IEEE Trans Comput C-36(3):264–276 (March)

    Article  Google Scholar 

  34. “The PowerPC Compiler Writers Guide”, IBM Microelectronics Division, published by Warthman Associates, ISBN 0-9649654-0-2

  35. Venkatasubramanian R, Hayes JP, Murray BT (2003) Low-cost on-line fault detection using control flow assertions. Proc. of the 9th IEEE International On-Line Testing Symposium (IOLTS’03), pp 137–143, July

  36. Venkatasubramanian R, Hayes JP, Murray BT (2003) Low-cost on-line fault detection using control flow assertions. Proc. of 9th IEEE On-Line Testing Symposium (IOLTS’03), Greece, pp 137–143, July

  37. Wilken K, Shen JP (1990) Continuous signature monitoring: low-cost concurrent detection of processor control errors. IEEE Trans Comput-Aided Des Integr Circuits Syst 9:629–641, June

    Article  Google Scholar 

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Correspondence to Mahdi Fazeli.

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Responsible Editor: N. A. Touba

This paper is the expanded version of the paper entitled as “A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems” which was published in the proceedings of DFT 2005, pp. 266–274.

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Fazeli, M., Farivar, R. & Miremadi, S.G. Error Detection Enhancement in PowerPC Architecture-based Embedded Processors. J Electron Test 24, 21–33 (2008). https://doi.org/10.1007/s10836-007-5017-3

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  • DOI: https://doi.org/10.1007/s10836-007-5017-3

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