1. Editorial

   • Vishwani D. Agrawal

   Editorial Introduction Pages: 5 - 5

2. Test Technology Technical Council Newsletter

   News Pages: 7 - 8

3. Foreword

   • Kozo Kinoshita

   Foreword Pages: 13 - 13

4. Guest Editorial

   • Kuen-Jong Lee
   • Chau-Chin Su

   Editorial Introduction Pages: 15 - 16

5. Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

   • Wei-Yu Chen
   • Sandeep K. Gupta
   • Melvin A. Breuer

   OriginalPaper Pages: 17 - 28

6. Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface

   • Yiorgos Makris
   • Jamison Collins
   • Alex Orailoğlu

   OriginalPaper Pages: 29 - 42

7. An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment

   • Wei-Lun Wang
   • Kuen-Jong Lee

   OriginalPaper Pages: 43 - 53

8. Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption

   • Michiko Inoue
   • Emil Gizdarski
   • Hideo Fujiwara

   OriginalPaper Pages: 55 - 62

9. State and Fault Information for Compaction-Based Test Generation

   • Ashish Giani
   • Shuo Sheng
   • Vishwani D. Agrawal

   OriginalPaper Pages: 63 - 72

10. TA-PSV—Timing Analysis for Partially Specified Vectors

    • Liang-Chi Chen
    • Sandeep K. Gupta
    • Melvin A. Breuer

    OriginalPaper Pages: 73 - 88

11. Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing

    • Chih-Wen Lu
    • Chung Len Lee
    • Jwu-E Chen

    OriginalPaper Pages: 89 - 97