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State and Fault Information for Compaction-Based Test Generation

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Abstract

We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vector compaction. Two types of techniques are considered. One is based on the new states a sequential circuit is driven into, and the other is based on the new faults that are detected between consecutive iterations of vector compaction. These data modify an otherwise random selection of vectors, to bias vector sequences that cause the circuit to reach new states, and cause previously undetected faults to be detected. The biased vectors, when used to extend the compacted test set, provide a more intelligent selection of vectors. The extended test set is then compacted. Repeated applications of state and fault analysis, vector generation and compaction produce significantly high fault coverage using relatively small computing resources. We obtained improvements in terms of higher fault coverage, fewer vectors for the same coverage, or smaller number of iterations and time required, consistently for several benchmark circuits.

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Authors and Affiliations

  1. Intel Corporation, Hillsboro, OR, 97124, USA

    Ashish Giani

  2. Bradley Department of Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, USA

    Shuo Sheng & Michael S. Hsiao

  3. Agere Systems, Murray Hill, NJ, 07974, USA

    Vishwani D. Agrawal

Authors
  1. Ashish Giani
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  2. Shuo Sheng
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  3. Michael S. Hsiao
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  4. Vishwani D. Agrawal
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Giani, A., Sheng, S., Hsiao, M.S. et al. State and Fault Information for Compaction-Based Test Generation. Journal of Electronic Testing 18, 63–72 (2002). https://doi.org/10.1023/A:1013780023643

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