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Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing

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Abstract

In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 × 107 gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Chi Nan University, Nantou Hsien, Taiwan, ROC

    Chih-Wen Lu, Chung Len Lee, Chauchin Su & Jwu-E Chen

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  1. Chih-Wen Lu
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  2. Chung Len Lee
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  3. Chauchin Su
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  4. Jwu-E Chen
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Lu, CW., Lee, C.L., Su, C. et al. Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. Journal of Electronic Testing 18, 89–97 (2002). https://doi.org/10.1023/A:1013784124552

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  • DOI: https://doi.org/10.1023/A:1013784124552

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