1. Editorial

   • Vishwani D. Agrawal

   Editorial Introduction Pages: 571 - 571

2. Logic Design Validation via Simulation and Automatic Test Pattern Generation

   • Hussain Al-asaad
   • John P. Hayes

   OriginalPaper Pages: 575 - 589

3. A Fault Tolerant Technique for FPGAs

   • John M. Emmert
   • Dinesh K. Bhatia

   OriginalPaper Pages: 591 - 606

4. Intermediacy Prediction for High Speed Berger Code Checkers

   • Cecilia Metra
   • Jien-Chung Lo

   OriginalPaper Pages: 607 - 615

5. Bridging Faults in Pipelined Circuits

   • M. Favalli
   • C. Metra

   OriginalPaper Pages: 617 - 629

6. Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study

   • André Ivanov
   • Vikram Devdas

   OriginalPaper Pages: 631 - 634

7. A New Method for Testing Re-Programmable PLAs

   • Charles E. Stroud
   • James R. Bailey
   • Johan R. Emmert

   OriginalPaper Pages: 635 - 640