Skip to main content
Log in

Intermediacy Prediction for High Speed Berger Code Checkers

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

    We’re sorry, something doesn't seem to be working properly.

    Please try refreshing the page. If that doesn't work, please contact support so we can address the problem.

Abstract

We present an intermediacy prediction method that can be used to designhigh speed checkers for Berger codes, as well as for any other unordered code. In the proposed method, the received information and check bits are processed simultaneously toward an intermediate result. A two-rail code checker is then used to compare the two versions of such an intermediate result. Recall that, in conventional checkers for unordered codes, the received check bits remain idle until the received information bits are converted to the re-generated check bits. Therefore, our proposed intermediacy prediction method allows a checker's speed improvement. We show the application of our method to two well-Bergercode checker architectural solutions: (1) the threshold function based implementation, and (2) the Berger code partitioning design. We have verified that, as expected, the proposed method can improve the detecting speed of these existing solutions with moderate or minimum increase, and sometimes decrease, in hardware complexity.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. M. Nicolaidis, “Scaling Deeper to Submicron: On-Line Testing to the Rescue,” in Proc. of IEEE Int. Test Conf., 1998, p. 1139.

  2. W.C. Carter and P.R. Schneider, “Design of Dynamically Checked Computers,” in Proc. IFIP '68, Edinburgh, Scotland, 1968, pp. 878–883.

  3. M.Y. Yen, W.K. Fuchs, and J.A. Abraham, “Designing for Concurrent Error Detection in VLSI: Application to a Microprogram Control Unit,” IEEE J. of Solid State Circuit, Vol. SC-22, pp. 595–605, Aug. 1987.

    Google Scholar 

  4. D.K. Pradhan and J.J. Stiffler, “Error-Correcting Codes and Self-Checking Circuits,” Computer, Vol.13, No. 3, pp. 27–37, March 1980.

    Google Scholar 

  5. M.J. Ashjaee and S.M. Reddy, “On Totally Self-Checking Checkers for Separable Codes,” IEEE Trans. Comput., Vol. C-26, pp. 737–744, Aug. 1977.

    Google Scholar 

  6. M.A. Marouf and A.D. Friedman, “Efficient Design of Self-Checking Checkers for Any m-out-of-n code,” IEEE Trans. Comput., Vol. C-27, pp. 482–490, June 1978.

    Google Scholar 

  7. J.C. Lo and S. Thanawastien, “The Design of Fast Totally Self-Checking Berger Code Checkers Based on Berger Code Partitioning,” in Proc. FTCS-19, June 1988, pp. 226–231.

  8. T.R.N. Rao, G.L. Feng, M.S. Kolluru, and J.C. Lo, “Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning,” IEEE Trans. Comput., Vol. 42, pp. 1020–1024, Aug. 1993.

    Google Scholar 

  9. C. Metra, M. Favalli, and B. Riccò, “Novel Berger Code Checker,” in Proc. of IEEE Int. Work. on Defect and Fault Tolerance in VLSI Systems, 1995, pp. 287–295.

  10. D. Pierce Jr. and P.K. Lala, “Modular Implementation of Efficient Self-Checking Checkers for the Berger Code,” J. of Electronic Testing: Theory and Applications (JETTA), Vol. 9, pp. 279–294, Dec. 1996.

    Google Scholar 

  11. C. Metra and J.-C. Lo, “Compact and High Speed Berger Code Checker,” in Proc. of 2nd IEEE Int. On-Line Testing Work., 1996, pp. 144–149.

  12. Y.-Y. Guo, J.-C. Lo, and C. Metra, “Fast and Area-Time Efficient Berger Code Checkers,” in Proc. of IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, 1997, pp. 110–118.

  13. S.J. Piestrak, “Design of Encoders and Self-Testing Checkers for Some Systematic Unidirectional Error Detecting Codes,” in Proc. of IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, 1997, pp. 119–127.

  14. S. Piestrak, “Design of Fast Self-Testing Checkers for a Class of Berger Codes,” IEEE Trans. Comput., Vol. C-36, pp. 629–634, May 1987.

    Google Scholar 

  15. X. Kavausianos and D. Nikolos, “Novel Single and Double Output TSC Berger Code Checker,” in Proc. of IEEE VLSI Test Symp., 1998, pp. 348–353.

  16. M. Nicolaidis, I. Jansch, and B. Courtois, “Strongly Code-Disjoint Checkers,” in Proc. of Int. Symp. Fault-Tolerant Comput., 1984, pp. 16–21.

  17. M. Nicolaidis, “Fault Secure Property Versus Strongly Code Disjoint Checkers,” IEEE Trans. on CAD, Vol. 13, No. 5, pp. 651–658, May 1994.

    Google Scholar 

  18. C. Metra and J.C. Lo, “General Design Method for VLSI High Speed Berger Code Checkers,” in Proc. of 4th IEEE Int. On-Line Testing Work., 1998, pp. 177–181.

  19. S. Piestrak, “The Minimal Test Set for Sorting Networks and the Use of Sorting Networks in Self-Testing Checkers for Unordered Codes,” in Proc. FTCS-20, June 1990, pp. 457–464.

  20. E.J. McCluskey, Logic Design Principle-With Emphasis on Testable Semicustom Circuits, Prentice Hall, Englewood Cliffs, NJ, 1986.

    Google Scholar 

  21. C. Metra, M. Favalli, and B. Riccò, “Highly Testable and Compact Single Output Comparator,” in Proc. of IEEE VLSI Test Symp., 1997, pp. 210–215.

  22. S. Piestrak, “Design of Self-Testing Checkers for Unidirectional Error Detecting Codes,” in Monographs No. 24, Oficyna Wyd. Polit. Wrocl., Wroclaw, 1995.

  23. K.E. Batcher, “Sorting Networks and Their Applications,” in Proc. 1968 SJCC, AFIPS, 1968, pp. 307–314.

  24. P.K. Lala, Fault Tolerant and Fault Testable Hardware Design, Prentice-Hall International, Englewood Cliffs, NJ, 1985.

    Google Scholar 

  25. C. Metra, M. Favalli, and B. Riccò, “Novel Implementation for Highly Testable Parity Code Checkers,” in Proc. of 4th IEEE Int. On-Line Testing Work, 1998, pp. 167–171.

  26. B. Bose, “On Unordered Codes,” IEEE Trans. Comput., Vol. 40, pp. 125–131, Feb. 1991.

    Google Scholar 

Download references

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Metra, C., Lo, JC. Intermediacy Prediction for High Speed Berger Code Checkers. Journal of Electronic Testing 16, 607–615 (2000). https://doi.org/10.1023/A:1008369203223

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008369203223

Navigation