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Parametric Study on Pressureless Sintering of Nanosilver Paste to Bond Large-Area (≥100 mm2) Power Chips at Low Temperatures for Electronic Packaging

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Abstract

We have developed a new kind of nanosilver paste by reducing the stress and strain of the drying process with the help of some organics to bond large-area (≥100 mm2) power chips without additional pressure. This new nanosilver paste contains nanoparticles and microparticles ranging from 0.02 μm to 2 μm. The effects of sintering temperature (T), heating rate (ν), and holding time for sintering (t) on the microstructure and mechanical properties of sintered silver joints were investigated by the Taguchi method. The various factors were assigned to an L16 (43) orthogonal array. The experimental results showed that neck formation was strongly dependent on the increase of the sintering temperature, while prolonging the holding time and decreasing the heating rate were beneficial to neck growth. The pore size distribution ranged from 0.03 μm2 to 1.6 μm2, and the larger pores (0.8 μm2 to 1.6 μm2) were more irregular and clustered along the interstices between particles. The shear strength increased with increased sintering temperature, prolonged holding time, and decreased heating rate due to smaller pore size and a more homogeneous pore distribution. The fatigue and tensile behaviors of pressureless-sintered silver joints were also compared with those of soldered SAC305 joints.

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Acknowledgements

The authors gratefully acknowledge financial support from the National Natural Science Foundation of China (No. 61334010), the Tianjin Municipal Natural Science Foundation (under Grants 13JCQNJC06600 and 13JCZDJC33600), the National Science & Technology Pillar Program (Grant No. 2013BAG02B01), and the National High Technology Research and Development Program of China (No. 2015AA034501). The work was supported by and corresponds to Dr. Yunhui Mei of Tianjin University.

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Fu, S., Mei, Y., Li, X. et al. Parametric Study on Pressureless Sintering of Nanosilver Paste to Bond Large-Area (≥100 mm2) Power Chips at Low Temperatures for Electronic Packaging. J. Electron. Mater. 44, 3973–3984 (2015). https://doi.org/10.1007/s11664-015-3842-1

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