Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes

Abstract

Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the viable solutions toward scaling down below sub-7nm technology nodes. In this work, we compare electrical performance, including variability studies of several horizontal nanosheet transistors toward transistor structure optimization. We explore the impacts of nanosheet width and thickness on the electrical performance and outline important design guidelines necessary for vertically stacked nanosheet FETs. An increase in the complexity of the stacked nanosheet structures can lead to significant device variability. Using numerical simulation, we study the characteristics fluctuations induced by the random discrete dopants (RDD) and metal grain granularity (MGG) in nanosheet gate-all-around (GAA) transistors. We use 3-D quantum-mechanically corrected transport models in the simulation. It is observed that the σV_TH due to MGG variability is 12% higher than RDD variability while the RDD variability strongly influences the I_ON. The statistical simulation results predict that the presence of combined variability due to RDD and MGG strongly influences the threshold voltage variation (σV_TH) in nanoscale devices. This approach may be applied to the different types of variability, the geometry of the device, including the vertical and lateral dimensions of the transistor, and biasing conditions.

1 Introduction

Stacked nanosheet FETs (SNSFETs) have been emerged as new innovative device architecture to replace fin-shaped FETs (FinFETs) due to their high current driving capabilities, excellent electrostatics control, and high-frequency operation [1,2,3]. SNSFETs provide a higher current per layout footprint because it has a large effective channel width (W_eff) per footprint compared to nanowire FETs or even stacked nanowire FETs [2, 4, 5]. The use of technologies below 22 nm leads to a complexity of increased design with more potential sources of variability. However, these miniaturized transistors suffer from the process and statistical variations, which significantly affect the overall performance of the circuit [6]. The manufacturing variation represents a random deviation from the specifications of typical design, which stimulates circuit degradation, abnormal power consumption, and diverging performance. Furthermore, as transistors scale down, the device to device variation also becomes important.

In SNSFETs, nanosheet width is not limited by fin pitch and fin quantization, giving more degree of freedom to achieve larger effective widths (W_eff) for circuit design [7]. W_eff significantly affects current drivability, electrostatics, and parasitic components. Advanced technologies are more likely to experience process variations such as line edge roughness (LER) and metal gate granularity (MGG). The variability of manufacturing represents a random deviation which changes the structure of the transistor, and therefore, changes the electrical properties of a circuit. For proper design optimization of NSFETs, it is essential to evaluate device design options. The process flow plays an important role in device design and its performance optimization [2]. Process variations of SNSFET have been investigated in terms of metal thickness variation, which includes intersheet spacing and metal thickness to minimize the threshold voltage, V_TH variability [8]. Many researchers have investigated the statistical variations of FinFETs and GAA-nanowire FETs and proposed various modeling frameworks for variability-aware design. The most significant statistical variations are random discrete dopants (RDD), metal gate granularity (MGG), and line edge roughness (LER) [9,10,11,12,13,14,15]. However, the intrinsic variation LER becomes insignificant due to the larger width of SNSFET compared to fin thickness in FinFETs [2]. According to Mittal et al., fin thickness do not represent the quantum confinement regime in the width direction [16]. Therefore, LER arising due to the lithography and etching process does not result in significant variability.

Although the use of metal as gate material is advantageous for controlling specific challenges, it changes grain orientations by generating different, randomly aligned work functions, which involves higher fluctuations in the work function. MGG of the gate induces work function variation (WFV), which causes V_TH variability in high-k/metal gate technology for sub-10 nm-technology nodes [17]. The WFV would also cause dc performance variations of SNSFETs; however, these have not been investigated in detail. The RDD-induced variations have been a dominant source of variability, which is not related to manufacturing technology. As the devices are scaled-down, the impact of the source/drain (S/D) parasitic resistance becomes very significant and dominantly affects the device performance. Consequently, the S/D critical dimension variations of SNSFETs have also been investigated [18]. In particular, the impacts of the S/D process variations, which include S/D epitaxy shape, depth, S/D length, and S/D doping concentration on the Si-FinFETs, have been addressed in several studies [19,20,21,22]. Still, the analysis of RDD-induced variations in the S/D extensions on SNSFETs has not been explored in detail. From a design perspective, these challenges require precise estimates of the circuit behavior, emphasizing the importance of indicating new design guidelines capable of handling these challenges to maintain the technology progress. In this work, the variation in width and thickness of nanosheet has been studied to propose a better design. The metal work function variation, and RDD-induced variations in the S/D extensions in SNSFETs, have also been explored in details. The main focus is to evaluate how the device variability can be accurately predicted in nanosheet GAA FETs and define guidelines that can be used by the device designers.

This manuscript is organized as follows: Section 2 describes the device specifications and simulation parameters. The performance of different device geometries is analyzed in Sect. 3. We address the SNSFET device random fluctuation induced by RDD and MGG via 3-D numerical device simulations. A statistical modeling approach is used to model the observed variability and identify the sources of variations in terms of the sensitivities to each source of variability. We investigate the random fluctuation considering MGG in conjunction with RDD in Sect. 4. The concluding remarks are presented in Sect. 5.

2 Device structure and simulation methodology

The simulated device SNSFET is a three-dimensional structure with 14 nm gate length, as shown in Fig. 1a. The cross-sectional view of three stacked nanosheets and the net doping concentration is shown in Fig. 1b and c, respectively. All the critical device geometry parameters are defined in Table 1. The width (W_NS) of SNSFET is ranging from 3 to 12 nm and thickness (H_NS) ranging from 4 to 6 nm. The channel is n-doped (N_D) with a doping concentration of 10¹⁶ cm⁻³, and the source/drain (S/D) extension regions are heavily p-doped (N_A) with a doping concentration of 10²⁰ cm⁻³. The gate oxide consists of SiO₂ and HfO₂ of thickness is 0.5 nm and 1.5 nm, respectively, titanium nitride (TiN) is used as the gate material. Considering the diverse requirements in device simulation, it is natural to ask for the level of confidence at which device simulation tools are useful for device development. To gain confidence in simulations of SNSFETs, we first simulate the reported experimental electrical characteristics of SNSFETs [2]. The structure used for 2D numerical simulation is shown in the inset of Fig. 2, and it is designed to match with actual SNSFETs used in this study. Figure 2 shows the calibration of the drain current of a three-stack SNSFET reported in reference [2] for V_D = 0.05 V and 0.7 V in log scale and linear scale. For calibration, L_g and H_NS are selected as 12 nm and 5 nm, respectively. The calibration results obtained from our simulations show a good agreement with the reported experimental data. The reproduction of the experimental characteristics of SNSFETs by using the physics-based models described below gives the device designers a high confidence level regarding the effectiveness and feasibility of the models used toward predictive simulations.

Fig. 1

a Schematic of SNSFETs (L_g = 14 nm), b the cross-sectional view of three stacked nanosheets and c Net doping concentration of SNSFET is shown

Table 1 Device details of SNSFETs

Fig. 2

Comparison of the simulated transfer characteristics with reported experimental data [from reference 2] in linear and log scale

The drift–diffusion (DD) model can be used to simulate the transportation inside the channel of the device with several limitations [23, 24]. To include the non-equilibrium transport phenomena, the electrostatic potential has to be calculated from the Poisson equation including quantum corrections combined with the current continuity equation for electrons to calculate the electron current density $\left({J}_{n}\left(r\right)\right)$

$$J_{n} \left( r \right) = \left| q \right|\mu_{n} \left( r \right)n\left( r \right)\nabla \left( {\phi_{n} \left( r \right)} \right)$$

(1)

$${\text{div}}\left( {J_{n} \left( r \right)} \right) = qR\left( r \right)$$

(2)

where ${\mu }_{n}\left(r\right)$ is the electron mobility and R(r) is the recombination term.

Density-gradient (DG) quantization model [25] considers the quantum confinement effects of the nanosheet channels were calculated self-consistently with the Poisson, drift–diffusion, and carrier continuity equations. The quantum corrected drift–diffusion carrier transport model is incorporated in MINIMOS-NT [26]. The DG quantum potential for electrons, V_DG(r) [27], is obtained as:

$$V_{{{\text{DG}}}} \left( r \right) = \frac{{2\left[ {b_{n} } \right] \nabla^{2} \left( {\sqrt {n\left( r \right)} } \right)}}{{\sqrt {n\left( r \right)} }} = \phi_{n} \left( r \right) - V_{cl} \left( r \right) + \frac{{k_{B} T}}{q}ln\left( {\frac{n\left( r \right)}{{n_{i} \left( r \right)}}} \right)$$

(3)

where $\left[ {b_{n} } \right] = \frac{{\hbar^{2} }}{{4qr_{n} }}\left( {\begin{array}{*{20}c} {1/m_{x} } & 0 & 0 \\ 0 & {1/m_{y} } & 0 \\ 0 & 0 & {1/m_{z} } \\ \end{array} } \right)$.

Here, $r = (x, y, z)$ is the spatial coordinate,${\phi }_{n}\left(r\right)$ is the electron quasi-Fermi potential, ${n}_{i}(r)$ is the intrinsic carrier concentration of electron and holes, ${V}_{cl}\left(r\right)$ is the classical electrostatic potential, ${k}_{B}, T, \mathrm{and} \hslash$ are the Boltzmann constant, the lattice temperature, and the reduced Planck constant, respectively, ${r}_{n}$ is the dimensionless parameter that accounts for statistical effects and ${m}_{x}, {m}_{y} \mathrm{and} {m}_{z}$ are the DG electron effective masses in the $x, y \mathrm{and} z$ directions, respectively. The distributions of electron current density contours for the simulated SNSFET at on-state and off-state are illustrated in Fig. 3. At on-state, due to the presence of V_GS, the electric field is generated all around the gate. The strength of net electric field is high in sidewalls compared to top and bottom wall of the gate. This results in such distribution of the carrier and current density as shown in Fig. 3.

Fig. 3

Electron current density contour at on-state and off-state for NSFET across the channel with W_NS = 12 nm and H_NS = 5 nm

The 3D numerical device simulation is analyzed using the quantum corrected drift–diffusion transport model. Shockley–Read–Hall and Auger recombination models are used for minority carrier recombination [28, 29]. Slotboom model for bandgap narrowing is considered [30]. The calibrated mobility models included in our simulation framework are high field saturation, Coulomb scattering, and inversion and accumulation. Lombardi mobility model is used to account for various geometric quantization effects like thickness-fluctuation, phonon, and surface roughness scattering [31].

3 Results and discussion

In this section, we have analyzed different NSFET configurations and the effect of process-induced variabilities RDD, MGG, and their combined impact on the performance of SNSFETs. A technology CAD simulation framework has been used to study the device performance variations.

3.1 Impact of nanosheet width and thickness on the performance of SNSFET

We compared and analyzed each NSFET configuration through threshold voltage (V_TH), ON-state drive current (I_ON), OFF-state leakage current (I_OFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL). The transfer characteristic (I_DV_GS) plot is analyzed by varying W_NS from 3 to 12 nm with fixed H_NS at 5 nm, as shown in Fig. 4a. It is observed that SNSFET provides an improvement in the drive current for higher nanosheet width due to larger effective channel width.

Fig. 4

a I_DV_GS of NSFETs having different W_NS at V_DS = 0.7 V. b I_ON, as a function of V_TH,sat for SNSFETs with W_NS = 3–12 nm at L_g = 8–14 nm. c I_OFF and d DIBL of NSFETs with different W_NS and H_NS

Figure 4b shows I_ON as a function of the V_TH,sat for SNSFETs with W_NS (3–12 nm) at L_g (8–14 nm). By reducing the gate length to 8 nm, the reduction of V_TH results in an increase of I_ON. The nanosheet width reduction also induces a higher V_TH,sat due to stronger confinement potential. It is also observed that the increase in I_ON is due to enhanced effective width. Figure 4c shows I_OFF as a function of W_NS for different H_NS at V_DS = 0.7 V. I_OFF also increases with increasing H_NS due to the reduction in potential barrier height, and it can be reduced by using thinner nanosheet. The variations of DIBL as a function of sheet width, which is shown in Fig. 4d, indicate the trade-off between sheet width, which dominates the intrinsic performance of the devices and the immunity to short channel effect (SCE).

Figures 5a and b show the impact of an increase in nanosheet width on SS and DIBL for different gate lengths, respectively. It is observed that the SS degradation at a gate length of 14 nm is marginal. However, an 11 mV/decade SS degradation is observed when the gate length reduces to 8 nm. SNSFETs with thinner width have smaller SS degradation due to enhanced gate control over the channel. Figure 5b shows DIBL has a similar trend with SS, and wider nanosheet provides higher DIBL. The impact of nanosheet width on the I_OFF and I_ON/I_OFF ratio is illustrated in Figs. 5c and d, respectively. It is observed that smaller nanosheet width provides a better I_ON/I_OFF ratio due to larger overdrive voltage. However, wider nanosheet provides larger I_ON and smaller I_OFF, so I_ON/I_OFF ratio gets better due to enhanced effective width. Figure 5d shows I_OFF increases with an increase in the nanosheet width, which can be mitigated by using thinner nanosheet. Large I_OFF degradation is observed when the gate length reduces from 14 to 8 nm. Finally, optimized SNSFET is presented considering maximum performance improvement with W_NS and H_NS of 12 nm and 6 nm, respectively. The I_ON, DIBL, and SS of presented SNSFET are 73.4 μA, 23.41 mV V⁻¹, and 67 mV/dec, respectively.

Fig. 5

a SS b DIBL c I_ON/I_OFF and d I_OFF as a function of W_NS for NSFETs having different L_g at V_DS = 0.7 V

3.2 Impact of random dopant fluctuation

The fluctuation of dopants can be used to analyze the impact of RDD in terms of their number and position. Figure 7 shows that the number of dopants follows Poisson distribution, and the location of dopants follows a uniform distribution. Based on the doping concentration, the dopant position is determined randomly. Here the dopant discretization is only executed in the source and drain extension regions [32,33,34]. Both position and dopant number variations affect the transfer characteristics and other device parameters. The discrete dopants are positioned in the device randomly, and the electrostatics associated with these random dopants are calculated by using the Sano method [35]. The number density of the discrete dopant is given by

$$n\left( r \right) = N_{f} \frac{{k_{c}^{3} }}{{2\pi^{2} }}\frac{{{\text{sin}}\left( {k_{c} r} \right) - \left( {k_{c} r} \right)\cos \left( {k_{c} r} \right)}}{{\left( {k_{c} r} \right)^{3} }}$$

(4)

where ${N}_{f}$ is the normalization factor, ${k}_{c}$ is the inverse of screening length, and $r$ is the distance from the discrete dopant. The screening length can be calculated by using Conwell–Weisskopf model [35, 36] and defined as ${k}_{c}\approx 2{\left({N}_{D/A}\right)}^{1/3}$ where ${N}_{D/A}$ represent donor/acceptor concentration.

I_DV_G plots of 14 nm gate length SNSFET are shown in Fig. 6, including discrete dopants fluctuations in the S/D extension regions at a drain bias of 50 mV and 0.7 V. The random dopant fluctuations in the source and drain extension induce the change in the V_TH, channel electrostatic potential, and source-channel potential barrier, which further results in I_ON variation in these regions. In RDD, the potential fluctuations due to donors in the source and drain extensions lead to large fluctuations in the source/drain access resistance which interpret an enhancement in the on-current variation. This effect will become increasingly important with further scaling because of the reduced volume of the access regions. From Fig. 7, it is observed that the figure of merits: V_TH, I_OFF, I_ON, and SS distributions subject to random dopants, i.e., RDD in the S/D extension. The mean (μ) and standard deviation (σ) of V_TH, I_OFF, I_ON, and SS are evaluated. An analytical model for V_TH, due to statistical dopant fluctuations has been reported for two-dimensional (2D) cross section in reference [37]. As slices of a 2D sheet can be integrated over the depth to give a 3D sheet, the use of the reported analytical model can be extended to compute V_TH for the 3D NSFET. The variance of dopant fluctuations in a sheet is the total number of dopants in the sheet. The number of dopants fluctuations per unit depth of cross section of the sheet of dopant is considered as ${N}_{\mathrm{sheet}}={N}_{A}{W}_{NS }{H}_{NS}$. Since ${dN}_{\mathrm{sheet}}\left(y\right)$ is the random variable for the area of ${W}_{\mathrm{NS} }{H}_{\mathrm{NS}}$ at a depth ‘y’ of the sheet, $\mathrm{d}{V}_{\mathrm{TH}}\left(y\right)$ becomes the random function in this sheet of depth $dy$ and can be expressed as [8]:

$${\text{d}}V_{{{\text{TH}}}} \left( y \right) = \frac{q}{{\varepsilon_{Si} }}\frac{{dN_{{{\text{sheet}}}} \left( y \right)}}{{W_{{{\text{NS}} }} \times H_{{{\text{NS}}}} }}y$$

(5)

where q is the electronic charge, ${\varepsilon }_{Si}$ is the relative permittivity of Si. $\mathrm{d}{V}_{\mathrm{TH}}\left(y\right)$ is solved for a particular value of dz along the longitudinal axis (z-axis). The solution of each cross section of the sheet further can be integrated over the entire length (L_eff) to consider the entire sheet. The V_TH of the SNSFET as a function of individual nanosheet can then be expressed as [38]:

$$V_{{{\text{TH}}}} = - \beta \eta \ln \left( {\mathop \sum \limits_{i = n} e^{{\frac{{ - V_{{{\text{TH}},i}} }}{\beta \eta }}} } \right)$$

(6)

where $\beta =\frac{\mathrm{kT}}{q}=26 mV$ at room temperature, $\eta =(\mathrm{SS}(\mathrm{mV}/\mathrm{dec})/60)$, and ${V}_{\mathrm{TH},i}$ is the threshold voltage of each sheet. Further, the impact of RDD-induced fluctuations on the $\upsigma$ (standard deviation) of V_TH can be expressed as:

$$\sigma V_{{\text{TH,RDD}}} \propto \frac{{\sqrt[4]{{N_{A} }}}}{{\sqrt {W_{{\text{NS }}} \times H_{{{\text{NS}}}} } }}$$

(7)

where ${N}_{A}$ denotes the average substrate dopant concentration.

Fig. 6

Transfer characteristics (I_DV_G) of 14 nm gate length SNSFET in linear and log scale including random discrete dopants in the S/D extension at a drain bias of a 50 mV and b 0.7 V

Fig. 7

Distributions of the impact of RDD-induced fluctuations in the S/D extension on a V_TH b I_OFF c I_ON and d SS for 200 different configurations

3.3 Impact of work function variations

Metal grain granularity due to the crystal orientation of the metal grain leads to the work function variations in high-k/metal gate nanoscale devices. The grains in the TiN metal gate region are generated by using the Voronoi approach [8, 39]. The grain position, shape, size, and orientation are taken into consideration in the simulation to create various metal-gate grain patterns. In the gate region, variation in the threshold voltage is based on the work functions of different crystallographic metal grains at the metal/oxide interface. The various metal grains have different orientations, the probability of its occurrence, the work function values, and the average grain sizes. The simulation of the polycrystalline grain structures uses the Poisson–Voronoi model. For the assignment of boundary conditions on the gate area, it is divided into grids, and each grid point is assigned with a random number generated following the Poisson distribution function. The Voronoi algorithm is used to define the grain boundaries and separate gate area into different grains. Figure 8 shows two different work function patterns generated with three different average grain sizes of 1, 3, and 5 nm. Poisson–Voronoi approach creates the appropriate metal grain area distribution, which is a similar distribution observed in the experimental results [40]. I_D-V_G plots of 14 nm gate length SNSFET for MGG variations are shown in Fig. 9. The $\sigma {V}_{\mathrm{TH}}$ distribution due to MGG can be related to grain size as:

$$\sigma V_{{{\text{TH}}}} \propto \frac{{\text{Grain size}}}{{\sqrt {W_{{{\text{eff}}}} \times L_{{{\text{eff}}}} } }}$$

(8)

Fig. 8

MGG profile shows the generated Voronoi pattern for grain sizes of 1, 3, and 5 nm of the 14 nm gate length SNSFET

Fig. 9

Transfer characteristics (I_DV_G) of 14 nm gate length SNSFET with MGG variations at an average grain size of a 1 nm, b 3 nm, and c 5 nm with 200 different probability configurations

The work function variability in the TiN metal grain is calculated by the Voronoi method [39, 41]. By employing two possible grain orientations < 200 > and < 111 > , for the TiN metal gate with a difference of 0.2 eV between the work function values. According to grain orientations, the effective work function and shape of each metal grain vary. In this work, we analyze for three different grain sizes 1, 3, and 5 nm and assume that the distribution of work function of TiN metal gate grain orientations is 4.55 (red color) and 4.35 eV (blue color) with 60% and 40% probability, respectively, as shown in Fig. 8. As the work function fluctuations consider only two different grains to calculate the effective grain number (N_{eff_grain}), which has been proposed in reference [41]. Therefore, N_{eff_grain} distributed on the metal surface of SNSFET is expressed as

$$N_{{{\text{plate\_region}} = }} \frac{{L_{g} \times 2 \times \pi \left\{ {H_{{{\text{NS}}}} /2 + \left( {W_{{{\text{NS}}}} - H_{{{\text{NS}}}} } \right)/\pi + T_{{{\text{OX}}}} } \right\}}}{{\pi \times \left( {\frac{{\text{Grain size}}}{2}} \right)^{2} }}$$

(9)

Considering ‘$i$’ is the number of grains having a work function of 4.55 eV and (${N}_{\mathrm{eff}\_\mathrm{grain}}-i$) is the number of grains having a work function of 4.35 eV. The metal gate work function can be calculated as the area-weighted average work function of all the grains present on the surface of the metal. The ${\sigma V}_{\mathrm{TH}}$ of work function variation shows a higher sensitivity to the number of grains or the size of the grain, as shown in Eq. (10). The probability distribution function (${P}_{i}$) is the probability of all grains distributed on the metal surface, as shown in Eq. (11). The metal gate work function (${\phi }_{i}$) is shown in Eq. (12):

$$\sigma V_{TH} = \sqrt {\frac{1}{{N_{{{\text{eff}}\_{\text{grain}}}} }}\left( {\mathop \sum \limits_{i = 0}^{{N_{{{\text{eff}}\_{\text{grain}}}} }} \left( {P_{i} \phi_{i}^{2} } \right) - \mathop \sum \limits_{i = 0}^{{N_{{{\text{eff}}\_{\text{grain}}}} }} \left( {P_{i} \phi_{i} } \right)^{2} } \right)}$$

(10)

$$P_{i} = \frac{{N_{{{\text{eff}}\_{\text{grain}}}} !}}{{i!\left( {N_{{{\text{eff}}\_{\text{grain}}}} - i} \right)!}}\left( {0.6} \right)^{i} \left( {0.4} \right)^{{N_{{{\text{eff}}\_{\text{grain}}}} - i}}$$

(11)

$$\phi_{i} = \frac{i}{{N_{{{\text{eff}}\_{\text{grain}}}} }}\left( {4.55 {\text{eV}}} \right) + \frac{{N_{{{\text{eff}}\_{\text{grain}}}} - i}}{{N_{{{\text{eff}}\_{\text{grain}}}} }}\left( {4.35 {\text{eV}}} \right)$$

(12)

The V_TH distribution, due to MGG, spreads more toward the head and tail regions with an increase in grain size is shown in Fig. 10. As nano-sized grains are considered, these distribution curves are very close [39]. This results in more deviation of the distribution shape from its normal distribution. As the grain size increases, the V_TH distribution due to MGG for both V_TH,Lin, and V_TH,Sat becomes more and more constrained at both the upper and lower tails alike to the behavior reported for bulk MOSFETs [42]. Due to the increase in the grain size, the total number of grains present in the gate surface decreases. As a result, the work function probability distribution diverges from the normal distribution and becomes discrete. Therefore, the increase in potential fluctuations will increase V_TH variability. With the increase in grain size from 1 to 5 nm, σV_TH increases by 161.2% and 151.2% in linear and saturation regions, respectively.

Fig. 10

Q-Q plot of V_TH distribution due to MGG for different metal gate grain sizes in a 50 mV and b 0.7 V of drain bias, respectively

Figure 11 shows that the σ value of V_TH, I_OFF, I_ON, and SS variations increases with larger grain size at both the linear and saturation mode in SNSFETs. It is observed that when the grain size decreases, the σ is reduced. This reduction is almost linear, dependent on the grain size for σV_TH, σI_ON, σI_OFF, and σSS. In Fig. 11, as the grain size is increased from 1 to 5 nm, the σV_TH is increased from 3.8 to 9.6 mV (a factor of 2). The standard deviation of the subthreshold characteristics is summarized in Table 2.

Fig. 11

Normalized distribution of V_TH, I_OFF, I_ON, and SS due to grain size variations for the 14 nm SNSFET at V_D = 0.7 V

Table 2 Footprint of grain size on standard deviations $\left(\sigma \right)$ of V_TH, I_OFF, I_ON, and SS at Vd = 0.7v

The effect of MGG on V_TH with different grain sizes, i.e., 1, 3, and 5 nm, is shown in Fig. 11. The $\upsigma {\mathrm{V}}_{\mathrm{TH}}$ in saturation mode is found to be 3.8 mV, 6.3 mV, and 9.6 mV for 1, 3, and 5 nm grain sizes, respectively. The effect of MGG on the V_TH is more noticeable in 5 nm grain size as the grain size is linearly dependent on the σV_TH. The V_TH variation is more severe when the grain size increase, as shown in Fig. 11. This is because of the large number of grains in the metal gate area, suppressing the WFV-induced σV_TH.

The DIBL variability as a function of V_TH for different grain sizes at low and high drain biases is shown in Fig. 12. The DIBL shows a minimal correlation with V_TH, mainly for grain sizes of 3 nm and 5 nm. The linear dependence between these variables is evaluated by the Pearson correlation coefficient (CC). Even the grain size reduces from 5 to 1 nm, the CC of the DIBL is larger for V_TH,Lin than V_TH,Sat. This trend has also been reported by Seoane et al. [43]. The significant separation between the linear and saturation drain biases for the 1 nm grain size is pronounced due to the DIBL effect.

Fig. 12

Scatter plots due to MGG variation in the 14 nm SNSFET for three different grain sizes: 1 nm, 3 nm, and 5 nm for the DIBL as a function of V_TH

3.4 3.4 Impact of combined variability sources

The effects of combined variability, i.e., RDD and MGG on the performance of SNSFETs, are shown in Fig. 13. Electrical transfer characteristics of 14 nm gate length SNSFET including combined (RDD + MGG) variation are shown in Fig. 13.

Fig. 13

I_DV_G plot for the scaled 14 nm gate length SNSFET including combined (RDD + MGG) variations at a drain bias of a 50 mV and b 0.7 V

The effect of fluctuation of random variations can be analyzed quantitatively using the statistical data. When the combined variability sources considered, it is observed that σV_TH increases by 12.7%, σSS increases by 54%, and σI_OFF decreases by 23.7% compared to RDD alone. When RDD is combined with MGG variability, they exhibit substantially different potential perspective and carrier distribution which results these quantitative changes. It is found that the impact of MGG variability on I_OFF is more effective than the combined variability analysis cases. However, the impact of RDD variability on I_ON has a stronger effect than MGG and combined cases.

The V_TH variability arises due to RDD and MGG, and the correlation plot between SS and V_TH is shown in Fig. 14. The linear regressions indicate the sensitivity of SS as a function of V_TH at a high drain bias. The SS shows negative correlations with V_TH, and the higher correlation is also observed in the combined variability effect. The higher the correlation coefficient (ρ) value, the less sensitive the variability is to a change in the drain bias.

Fig. 14

Scatter plots showing the correlation between SS and V_TH considering the impact of RDD and MGG variability in SNSFET at V_D = 0.7 V

Figure 15 shows the quantile–quantile plot of the distribution of SS due to the impact of the RDD and MGG variability sources, which follow a Gaussian distribution entirely. An increase in the σSS is due to combined variability sources and increases by 55.6% and 58.8% compared to MGG and RDD alone, respectively. The spread due to combined statistical variability increases and departs further from the normal distribution, as shown in Fig. 15.

Fig. 15

Statistical distribution of SS using a quantile plot for RDD and MGG variability sources at high drain bias

Figure 16 shows the correlation and distribution between the device performance variations (V_TH, I_OFF, I_ON, and DIBL) summarize in terms of scatter plots and correlation coefficients. I_OFF shows strong negative correlations with V_TH (ρ = -0.98) for combined variability sources. Besides, the V_TH and I_ON are negatively correlated with ρ =  0.67 but less compared to the ρ value between V_TH and I_OFF. Positively correlated are I_OFF and I_ON with a ρ =  0.63. The DIBL shows negative correlations with V_TH. However, the relationship between DIBL and other variations are comparatively weak. It can be observed that the changes in DIBL are more pronounced in the combined case compared to MGG and RDD separately. Due to the MGG variation, the drain end channel barrier is lower due to the drain field, which results in surface potential variation. Therefore, DIBL exhibits considerable variation.

Fig. 16

Correlations between the device performance variations for SNSFETs with combined sources of statistical variability. The correlation scatter plots and correlation coefficients at high drain bias are also listed in the table

4 Conclusions

We have analyzed the DC performances of sub-7nm node SNSFETs having different geometrical structures to study their impacts on the various nanosheet transistor parameters. The wide NSFET results in improved I_ON because of larger effective widths per footprint. I_OFF also increases with increase in the sheet width and this can be alleviated by using thinner nanosheet. DIBL is minimum for thinner nanosheet provided by enhanced gate control over the channel. SNSFETs provides more freedom for power-performance optimization due to the fine-tuning of W_NS. It is also evident that reducing the gate length can increase the drive current. I_OFF goes down drastically while scaling gate length from 14 to 8 nm in NSFET. We have also studied the intrinsic fluctuations including RDD, MGG and combined effect by 3D TCAD simulation. We have observed that the MGG sources predominantly affect the V_TH variability. We find that the σV_TH due to MGG variability is 12% higher than RDD variability. MGG-induced standard deviation shows linear reduction when the grain size decreases. The RDD sources strongly influence the I_ON variations because of access resistance variations. Furthermore, the combined sources of variability influence both the V_TH and SS variability. Finally, it is concluded that SNSFETs with larger width induces higher on-state drive current and smaller metal grains to improve device statistical variability immunity for future sub-7nm node devices.