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Optimization of Dual Material Based Dielectric Modulated Heterojunction Double Gate Tunnel FETs with Noise Reduction Analysis for High Frequency Applications

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Abstract

This study reveals the effect of variations in process parameters on the noise performance of dual gate Tunnel Field Effect Transistor (SMDGTFET), hetero dielectric Tunnel Field Effect Transistor (SMHDGTFET), dual metal gate Tunnel Field Effect Transistor (DMHDGTFET) and heterojunction dual metal gate Tunnel Field Effect Transistor (SiGe-DMHDGTFET), as previously proposed in the literature (Vedvrat et al. in Silicon 16:1297–1308, 2023). The noise characteristics, including the minimum noise figure (NFmin) and the optimum source impedance (Zopt), are examined in this work. This study also considers the statistical methods of auto-correlation aspects (< V1.V1* > / < V2.V2* >) and cross-correlation aspect (< V1.V2* >), due to the unpredictable nature of noise. We compare and study the four structures' analog characteristics as well as the effects of varying multiple structural design parameters on these characteristics in order to comprehend the structures' performance. Structure design elements including electric field, carrier concentration, surface potential, and carrier mobility explain the structure's internal mechanics. According to the performance assessment, the heterojunction dual metal hetero dielectric dual gate Tunnel FET (SiGe-DMHDGTFET), offers enhanced noise performance characteristics when the structure's channel length is reduced.

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Acknowledgements

The authors express their gratitude to Integral University, Lucknow, Uttar Pradesh, India, for giving them with the mcn number IU/R&D/2024-MCN0002486 for their current research work.

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The author(s) received no financial support for the research, authorship, and/or publication of this article.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Faculty of Engineering and Information Technology, Integral University, Lucknow, Uttar Pradesh, India

    Vedvrat & Mohd Yusuf Yasin

  2. Department of Electronics and Communication Engineering, Pranveer Singh Institute of Technology, Kanpur, Uttar Pradesh, India

    Vedvrat

  3. Department of Technical Education, Dr. A.P.J. Abdul Kalam Technical University, Lucknow, Uttar Pradesh, India

    Digvijay Pandey

Authors
  1. Vedvrat
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  3. Digvijay Pandey
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Contributions

Vedvrat: Conceptualization, Methodology, TCAD Software, Data curation, Analysis and Interpretation of data, Writing- Original draft preparation, Visualization, Investigation, Validation.

Mohd Yusuf Yasin: Supervision, review, revision and editing.

Digvijay Pandey: Revision and editing.

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Correspondence to Vedvrat.

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Vedvrat, Yasin, M.Y. & Pandey, D. Optimization of Dual Material Based Dielectric Modulated Heterojunction Double Gate Tunnel FETs with Noise Reduction Analysis for High Frequency Applications. Silicon (2024). https://doi.org/10.1007/s12633-024-02987-w

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